Searched refs:physymclk (Results 1 – 9 of 9) sorted by relevance
457 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg31_set_physymclk()464 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg31_set_physymclk()474 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg31_set_physymclk()481 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg31_set_physymclk()491 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg31_set_physymclk()498 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg31_set_physymclk()508 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg31_set_physymclk()515 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg31_set_physymclk()525 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg31_set_physymclk()532 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg31_set_physymclk()[all …]
282 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()289 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()299 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()306 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()316 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()323 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()333 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()340 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg401_set_physymclk()725 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) { in dccg401_init()
308 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg314_init()
235 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk && enable) in dccg35_set_physymclk_rcg()1515 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dccg35_set_physymclk_root_clock_gating()
701 bool physymclk: 1; member
485 if (!hws->ctx->dc->debug.root_clock_optimization.bits.physymclk) in dcn35_physymclk_root_clock_control()
922 .physymclk = true,
741 .physymclk = false,
761 .physymclk = false,