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Searched refs:phyclk_d32_mhz (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn321/
Ddcn321_fpu.c115 .phyclk_d32_mhz = 313.0,
431 entry.phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; in build_synthetic_soc_states()
852 dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; in dcn321_update_bw_bounding_box_fpu()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_mode_structs.h162 double phyclk_d32_mhz; member
Ddisplay_mode_vba.c400 mode_lib->vba.PHYCLKD32PerState[i] = soc->clock_limits[i].phyclk_d32_mhz; in fetch_socbb_params()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/
Ddml2_translation_helper.c361 p->in_states->state_array[0].phyclk_d32_mhz = 625; in dml2_init_soc_states()
397 p->in_states->state_array[0].phyclk_d32_mhz = 313; in dml2_init_soc_states()
432 p->in_states->state_array[0].phyclk_d32_mhz = 625; in dml2_init_soc_states()
684 out->state_array[i].phyclk_d32_mhz = dc->dml.soc.clock_limits[i].phyclk_d32_mhz; in dml2_translate_soc_states()
Ddisplay_mode_util.c627 dml_print("DML: state_bbox: phyclk_d32_mhz = %f\n", state->phyclk_d32_mhz); in dml_print_soc_state_bounding_box()
Ddisplay_mode_core_structs.h271 dml_float_t phyclk_d32_mhz; member
Ddisplay_mode_core.c7094 mode_lib->ms.state.phyclk_d32_mhz, in dml_core_mode_support()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/
Ddcn32_fpu.c136 .phyclk_d32_mhz = 625.0,
2883 entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; in build_synthetic_soc_states()
3296 dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; in dcn32_update_bw_bounding_box_fpu()