Searched refs:pcie_speed_table (Results 1 – 10 of 10) sorted by relevance
/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
D | smu7_hwmgr.c | 662 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, in smu7_setup_default_pcie_table() 673 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, in smu7_setup_default_pcie_table() 679 data->dpm_table.pcie_speed_table.count = max_entry - 1; in smu7_setup_default_pcie_table() 683 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, in smu7_setup_default_pcie_table() 688 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, in smu7_setup_default_pcie_table() 693 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, in smu7_setup_default_pcie_table() 698 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, in smu7_setup_default_pcie_table() 703 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, in smu7_setup_default_pcie_table() 708 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, in smu7_setup_default_pcie_table() 714 data->dpm_table.pcie_speed_table.count = 6; in smu7_setup_default_pcie_table() [all …]
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D | smu7_hwmgr.h | 106 struct smu7_single_dpm_table pcie_speed_table; member
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/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
D | vegam_smumgr.c | 579 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in vegam_populate_smc_link_level() 581 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in vegam_populate_smc_link_level() 583 dpm_table->pcie_speed_table.dpm_levels[i].param1); in vegam_populate_smc_link_level() 591 (uint8_t)dpm_table->pcie_speed_table.count; in vegam_populate_smc_link_level() 595 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in vegam_populate_smc_link_level() 872 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in vegam_populate_all_graphic_levels() 2034 PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1, in vegam_init_smc_table() 2038 hw_data->dpm_table.pcie_speed_table.count; in vegam_init_smc_table() 2103 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) { in vegam_init_smc_table()
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D | polaris10_smumgr.c | 825 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in polaris10_populate_smc_link_level() 827 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in polaris10_populate_smc_link_level() 829 dpm_table->pcie_speed_table.dpm_levels[i].param1); in polaris10_populate_smc_link_level() 837 (uint8_t)dpm_table->pcie_speed_table.count; in polaris10_populate_smc_link_level() 841 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in polaris10_populate_smc_link_level() 1044 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in polaris10_populate_all_graphic_levels() 2030 table->PCIeBootLinkLevel = hw_data->dpm_table.pcie_speed_table.count; in polaris10_init_smc_table() 2093 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) { in polaris10_init_smc_table()
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D | tonga_smumgr.c | 515 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in tonga_populate_smc_link_level() 517 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in tonga_populate_smc_link_level() 519 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in tonga_populate_smc_link_level() 531 (uint8_t)dpm_table->pcie_speed_table.count; in tonga_populate_smc_link_level() 533 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in tonga_populate_smc_link_level() 693 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count; in tonga_populate_all_graphic_levels() 2346 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count), in tonga_init_smc_table() 2350 table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count); in tonga_init_smc_table()
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D | fiji_smumgr.c | 836 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in fiji_populate_smc_link_level() 838 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in fiji_populate_smc_link_level() 840 dpm_table->pcie_speed_table.dpm_levels[i].param1); in fiji_populate_smc_link_level() 848 (uint8_t)dpm_table->pcie_speed_table.count; in fiji_populate_smc_link_level() 850 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in fiji_populate_smc_link_level() 1008 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count; in fiji_populate_all_graphic_levels()
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D | ci_smumgr.c | 1005 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in ci_populate_smc_link_level() 1007 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level() 1009 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level() 1016 (uint8_t)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level() 1018 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in ci_populate_smc_link_level() 2054 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count), in ci_init_smc_table() 2058 table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count; in ci_init_smc_table()
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D | iceland_smumgr.c | 772 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in iceland_populate_smc_link_level() 774 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in iceland_populate_smc_link_level() 776 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level() 788 (uint8_t)dpm_table->pcie_speed_table.count; in iceland_populate_smc_link_level() 790 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in iceland_populate_smc_link_level()
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/linux-6.12.1/drivers/gpu/drm/radeon/ |
D | ci_dpm.h | 71 struct ci_single_dpm_table pcie_speed_table; member
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D | ci_dpm.c | 2589 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) { in ci_populate_smc_link_level() 2591 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level() 2593 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level() 2599 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level() 2601 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in ci_populate_smc_link_level() 3365 &pi->dpm_table.pcie_speed_table, in ci_setup_default_pcie_tables() 3369 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables() 3373 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables() 3376 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, in ci_setup_default_pcie_tables() 3379 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, in ci_setup_default_pcie_tables() [all …]
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