Searched refs:pcie_regs (Results 1 – 3 of 3) sorted by relevance
764 struct amdgpu_regs_pcie_v1_0 *pcie_regs; in aqua_vanjaram_read_pcie_state() local775 amdgpu_reginst_size(1, sizeof(*pcie_regs), NUM_PCIE_SMN_REGS); in aqua_vanjaram_read_pcie_state()780 pcie_regs = (struct amdgpu_regs_pcie_v1_0 *)((uint8_t *)buf + in aqua_vanjaram_read_pcie_state()782 pcie_regs->inst_header.instance = 0; in aqua_vanjaram_read_pcie_state()783 pcie_regs->inst_header.state = AMDGPU_INST_S_OK; in aqua_vanjaram_read_pcie_state()784 pcie_regs->inst_header.num_smn_regs = NUM_PCIE_SMN_REGS; in aqua_vanjaram_read_pcie_state()786 reg_data = pcie_regs->smn_reg_values; in aqua_vanjaram_read_pcie_state()802 &pcie_regs->device_status); in aqua_vanjaram_read_pcie_state()804 &pcie_regs->link_status); in aqua_vanjaram_read_pcie_state()809 &pcie_regs->pcie_corr_err_status); in aqua_vanjaram_read_pcie_state()[all …]
93 __be32 pcie_regs[4]; member132 __be32 pcie_regs[4]; member171 __be32 pcie_regs[4]; member
1378 fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg)); in qla25xx_fw_dump()1380 fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg)); in qla25xx_fw_dump()1382 fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg)); in qla25xx_fw_dump()1383 fw->pcie_regs[3] = htonl(rd_reg_dword(®->iobase_window)); in qla25xx_fw_dump()1689 fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg)); in qla81xx_fw_dump()1691 fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg)); in qla81xx_fw_dump()1693 fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg)); in qla81xx_fw_dump()1694 fw->pcie_regs[3] = htonl(rd_reg_dword(®->iobase_window)); in qla81xx_fw_dump()2024 fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg)); in qla83xx_fw_dump()2026 fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg)); in qla83xx_fw_dump()[all …]