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Searched refs:par (Results 1 – 25 of 446) sorted by relevance

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/linux-6.12.1/drivers/video/fbdev/nvidia/
Dnv_setup.c60 void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value) in NVWriteCrtc() argument
62 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); in NVWriteCrtc()
63 VGA_WR08(par->PCIO, par->IOBase + 0x05, value); in NVWriteCrtc()
65 u8 NVReadCrtc(struct nvidia_par *par, u8 index) in NVReadCrtc() argument
67 VGA_WR08(par->PCIO, par->IOBase + 0x04, index); in NVReadCrtc()
68 return (VGA_RD08(par->PCIO, par->IOBase + 0x05)); in NVReadCrtc()
70 void NVWriteGr(struct nvidia_par *par, u8 index, u8 value) in NVWriteGr() argument
72 VGA_WR08(par->PVIO, VGA_GFX_I, index); in NVWriteGr()
73 VGA_WR08(par->PVIO, VGA_GFX_D, value); in NVWriteGr()
75 u8 NVReadGr(struct nvidia_par *par, u8 index) in NVReadGr() argument
[all …]
Dnv_hw.c57 void NVLockUnlock(struct nvidia_par *par, int Lock) in NVLockUnlock() argument
61 VGA_WR08(par->PCIO, 0x3D4, 0x1F); in NVLockUnlock()
62 VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57); in NVLockUnlock()
64 VGA_WR08(par->PCIO, 0x3D4, 0x11); in NVLockUnlock()
65 cr11 = VGA_RD08(par->PCIO, 0x3D5); in NVLockUnlock()
70 VGA_WR08(par->PCIO, 0x3D5, cr11); in NVLockUnlock()
73 int NVShowHideCursor(struct nvidia_par *par, int ShowHide) in NVShowHideCursor() argument
75 int cur = par->CurrentState->cursor1; in NVShowHideCursor()
77 par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) | in NVShowHideCursor()
79 VGA_WR08(par->PCIO, 0x3D4, 0x31); in NVShowHideCursor()
[all …]
Dnv_accel.c76 struct nvidia_par *par = info->par; in nvidiafb_safe_mode() local
80 par->lockup = 1; in nvidiafb_safe_mode()
85 struct nvidia_par *par = info->par; in NVFlush() local
88 while (--count && READ_GET(par) != par->dmaPut) ; in NVFlush()
98 struct nvidia_par *par = info->par; in NVSync() local
101 while (--count && NV_RD32(par->PGRAPH, 0x0700)) ; in NVSync()
109 static void NVDmaKickoff(struct nvidia_par *par) in NVDmaKickoff() argument
111 if (par->dmaCurrent != par->dmaPut) { in NVDmaKickoff()
112 par->dmaPut = par->dmaCurrent; in NVDmaKickoff()
113 WRITE_PUT(par, par->dmaPut); in NVDmaKickoff()
[all …]
/linux-6.12.1/drivers/video/fbdev/savage/
Dsavagefb_driver.c81 static void vgaHWSeqReset(struct savagefb_par *par, int start) in vgaHWSeqReset() argument
84 VGAwSEQ(0x00, 0x01, par); /* Synchronous Reset */ in vgaHWSeqReset()
86 VGAwSEQ(0x00, 0x03, par); /* End Reset */ in vgaHWSeqReset()
89 static void vgaHWProtect(struct savagefb_par *par, int on) in vgaHWProtect() argument
97 tmp = VGArSEQ(0x01, par); in vgaHWProtect()
99 vgaHWSeqReset(par, 1); /* start synchronous reset */ in vgaHWProtect()
100 VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */ in vgaHWProtect()
102 VGAenablePalette(par); in vgaHWProtect()
108 tmp = VGArSEQ(0x01, par); in vgaHWProtect()
110 VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */ in vgaHWProtect()
[all …]
/linux-6.12.1/drivers/staging/fbtft/
Dfb_ra8875.c17 static int write_spi(struct fbtft_par *par, void *buf, size_t len) in write_spi() argument
26 fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len, in write_spi()
29 if (!par->spi) { in write_spi()
30 dev_err(par->info->device, in write_spi()
37 return spi_sync(par->spi, &m); in write_spi()
40 static int init_display(struct fbtft_par *par) in init_display() argument
42 gpiod_set_value(par->gpio.dc, 1); in init_display()
44 par->fbtftops.reset(par); in init_display()
46 if ((par->info->var.xres == 320) && (par->info->var.yres == 240)) { in init_display()
48 write_reg(par, 0x88, 0x0A); in init_display()
[all …]
Dfb_bd663474.c24 static int init_display(struct fbtft_par *par) in init_display() argument
26 par->fbtftops.reset(par); in init_display()
31 write_reg(par, 0x000, 0x0001); /*oscillator 0: stop, 1: operation */ in init_display()
35 write_reg(par, 0x100, 0x0000); /* power supply setup */ in init_display()
36 write_reg(par, 0x101, 0x0000); in init_display()
37 write_reg(par, 0x102, 0x3110); in init_display()
38 write_reg(par, 0x103, 0xe200); in init_display()
39 write_reg(par, 0x110, 0x009d); in init_display()
40 write_reg(par, 0x111, 0x0022); in init_display()
41 write_reg(par, 0x100, 0x0120); in init_display()
[all …]
Dfb_ili9320.c22 static unsigned int read_devicecode(struct fbtft_par *par) in read_devicecode() argument
26 write_reg(par, 0x0000); in read_devicecode()
27 par->fbtftops.read(par, rxbuf, 4); in read_devicecode()
31 static int init_display(struct fbtft_par *par) in init_display() argument
35 par->fbtftops.reset(par); in init_display()
37 devcode = read_devicecode(par); in init_display()
39 dev_warn(par->info->device, in init_display()
47 write_reg(par, 0x00E5, 0x8000); in init_display()
50 write_reg(par, 0x0000, 0x0001); in init_display()
53 write_reg(par, 0x0001, 0x0100); in init_display()
[all …]
Dfb_upd161704.c24 static int init_display(struct fbtft_par *par) in init_display() argument
26 par->fbtftops.reset(par); in init_display()
31 write_reg(par, 0x0003, 0x0001); /* Soft reset */ in init_display()
34 write_reg(par, 0x003A, 0x0001); /*Oscillator 0: stop, 1: operation */ in init_display()
38 write_reg(par, 0x0024, 0x007B); /* amplitude setting */ in init_display()
40 write_reg(par, 0x0025, 0x003B); /* amplitude setting */ in init_display()
41 write_reg(par, 0x0026, 0x0034); /* amplitude setting */ in init_display()
43 write_reg(par, 0x0027, 0x0004); /* amplitude setting */ in init_display()
44 write_reg(par, 0x0052, 0x0025); /* circuit setting 1 */ in init_display()
46 write_reg(par, 0x0053, 0x0033); /* circuit setting 2 */ in init_display()
[all …]
Dfb_s6d1121.c27 static int init_display(struct fbtft_par *par) in init_display() argument
29 par->fbtftops.reset(par); in init_display()
33 write_reg(par, 0x0011, 0x2004); in init_display()
34 write_reg(par, 0x0013, 0xCC00); in init_display()
35 write_reg(par, 0x0015, 0x2600); in init_display()
36 write_reg(par, 0x0014, 0x252A); in init_display()
37 write_reg(par, 0x0012, 0x0033); in init_display()
38 write_reg(par, 0x0013, 0xCC04); in init_display()
39 write_reg(par, 0x0013, 0xCC06); in init_display()
40 write_reg(par, 0x0013, 0xCC4F); in init_display()
[all …]
Dfb_ili9325.c83 static int init_display(struct fbtft_par *par) in init_display() argument
85 par->fbtftops.reset(par); in init_display()
96 write_reg(par, 0x00E3, 0x3008); /* Set internal timing */ in init_display()
97 write_reg(par, 0x00E7, 0x0012); /* Set internal timing */ in init_display()
98 write_reg(par, 0x00EF, 0x1231); /* Set internal timing */ in init_display()
99 write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ in init_display()
100 write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */ in init_display()
101 write_reg(par, 0x0004, 0x0000); /* Resize register */ in init_display()
102 write_reg(par, 0x0008, 0x0207); /* set the back porch and front porch */ in init_display()
103 write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */ in init_display()
[all …]
Dfb_ssd1306.c32 static int init_display(struct fbtft_par *par) in init_display() argument
34 par->fbtftops.reset(par); in init_display()
36 if (par->gamma.curves[0] == 0) { in init_display()
37 mutex_lock(&par->gamma.lock); in init_display()
38 if (par->info->var.yres == 64) in init_display()
39 par->gamma.curves[0] = 0xCF; in init_display()
41 par->gamma.curves[0] = 0x8F; in init_display()
42 mutex_unlock(&par->gamma.lock); in init_display()
46 write_reg(par, 0xAE); in init_display()
49 write_reg(par, 0xD5); in init_display()
[all …]
Dfb_ssd1289.c26 static int init_display(struct fbtft_par *par) in init_display() argument
28 par->fbtftops.reset(par); in init_display()
30 write_reg(par, 0x00, 0x0001); in init_display()
31 write_reg(par, 0x03, 0xA8A4); in init_display()
32 write_reg(par, 0x0C, 0x0000); in init_display()
33 write_reg(par, 0x0D, 0x080C); in init_display()
34 write_reg(par, 0x0E, 0x2B00); in init_display()
35 write_reg(par, 0x1E, 0x00B7); in init_display()
36 write_reg(par, 0x01, in init_display()
37 BIT(13) | (par->bgr << 11) | BIT(9) | (HEIGHT - 1)); in init_display()
[all …]
Dfb_hx8347d.c23 static int init_display(struct fbtft_par *par) in init_display() argument
25 par->fbtftops.reset(par); in init_display()
28 write_reg(par, 0xEA, 0x00); in init_display()
29 write_reg(par, 0xEB, 0x20); in init_display()
30 write_reg(par, 0xEC, 0x0C); in init_display()
31 write_reg(par, 0xED, 0xC4); in init_display()
32 write_reg(par, 0xE8, 0x40); in init_display()
33 write_reg(par, 0xE9, 0x38); in init_display()
34 write_reg(par, 0xF1, 0x01); in init_display()
35 write_reg(par, 0xF2, 0x10); in init_display()
[all …]
Dfb_ssd1305.c33 static int init_display(struct fbtft_par *par) in init_display() argument
35 par->fbtftops.reset(par); in init_display()
37 if (par->gamma.curves[0] == 0) { in init_display()
38 mutex_lock(&par->gamma.lock); in init_display()
39 if (par->info->var.yres == 64) in init_display()
40 par->gamma.curves[0] = 0xCF; in init_display()
42 par->gamma.curves[0] = 0x8F; in init_display()
43 mutex_unlock(&par->gamma.lock); in init_display()
47 write_reg(par, 0xAE); in init_display()
50 write_reg(par, 0xD5); in init_display()
[all …]
Dfbtft-core.c37 int fbtft_write_buf_dc(struct fbtft_par *par, void *buf, size_t len, int dc) in fbtft_write_buf_dc() argument
41 gpiod_set_value(par->gpio.dc, dc); in fbtft_write_buf_dc()
43 ret = par->fbtftops.write(par, buf, len); in fbtft_write_buf_dc()
45 dev_err(par->info->device, in fbtft_write_buf_dc()
73 static int fbtft_request_one_gpio(struct fbtft_par *par, in fbtft_request_one_gpio() argument
77 struct device *dev = par->info->device; in fbtft_request_one_gpio()
84 fbtft_par_dbg(DEBUG_REQUEST_GPIOS, par, "%s: '%s' GPIO\n", in fbtft_request_one_gpio()
90 static int fbtft_request_gpios(struct fbtft_par *par) in fbtft_request_gpios() argument
95 ret = fbtft_request_one_gpio(par, "reset", 0, &par->gpio.reset); in fbtft_request_gpios()
98 ret = fbtft_request_one_gpio(par, "dc", 0, &par->gpio.dc); in fbtft_request_gpios()
[all …]
/linux-6.12.1/drivers/video/fbdev/
Dbroadsheetfb.c119 static void broadsheet_gpio_issue_data(struct broadsheetfb_par *par, u16 data) in broadsheet_gpio_issue_data() argument
121 par->board->set_ctl(par, BS_WR, 0); in broadsheet_gpio_issue_data()
122 par->board->set_hdb(par, data); in broadsheet_gpio_issue_data()
123 par->board->set_ctl(par, BS_WR, 1); in broadsheet_gpio_issue_data()
126 static void broadsheet_gpio_issue_cmd(struct broadsheetfb_par *par, u16 data) in broadsheet_gpio_issue_cmd() argument
128 par->board->set_ctl(par, BS_DC, 0); in broadsheet_gpio_issue_cmd()
129 broadsheet_gpio_issue_data(par, data); in broadsheet_gpio_issue_cmd()
132 static void broadsheet_gpio_send_command(struct broadsheetfb_par *par, u16 data) in broadsheet_gpio_send_command() argument
134 par->board->wait_for_rdy(par); in broadsheet_gpio_send_command()
136 par->board->set_ctl(par, BS_CS, 0); in broadsheet_gpio_send_command()
[all …]
Dssd1307fb.c160 static int ssd1307fb_set_col_range(struct ssd1307fb_par *par, u8 col_start, in ssd1307fb_set_col_range() argument
166 if (col_start == par->col_start && col_end == par->col_end) in ssd1307fb_set_col_range()
169 ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_COL_RANGE); in ssd1307fb_set_col_range()
173 ret = ssd1307fb_write_cmd(par->client, col_start); in ssd1307fb_set_col_range()
177 ret = ssd1307fb_write_cmd(par->client, col_end); in ssd1307fb_set_col_range()
181 par->col_start = col_start; in ssd1307fb_set_col_range()
182 par->col_end = col_end; in ssd1307fb_set_col_range()
186 static int ssd1307fb_set_page_range(struct ssd1307fb_par *par, u8 page_start, in ssd1307fb_set_page_range() argument
192 if (page_start == par->page_start && page_end == par->page_end) in ssd1307fb_set_page_range()
195 ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_PAGE_RANGE); in ssd1307fb_set_page_range()
[all …]
Di740fb.c96 static inline void i740outb(struct i740fb_par *par, u16 port, u8 val) in i740outb() argument
98 vga_mm_w(par->regs, port, val); in i740outb()
100 static inline u8 i740inb(struct i740fb_par *par, u16 port) in i740inb() argument
102 return vga_mm_r(par->regs, port); in i740inb()
104 static inline void i740outreg(struct i740fb_par *par, u16 port, u8 reg, u8 val) in i740outreg() argument
106 vga_mm_w_fast(par->regs, port, reg, val); in i740outreg()
108 static inline u8 i740inreg(struct i740fb_par *par, u16 port, u8 reg) in i740inreg() argument
110 vga_mm_w(par->regs, port, reg); in i740inreg()
111 return vga_mm_r(par->regs, port+1); in i740inreg()
113 static inline void i740outreg_mask(struct i740fb_par *par, u16 port, u8 reg, in i740outreg_mask() argument
[all …]
Ds3fb.c192 static u8 s3fb_ddc_read(struct s3fb_info *par) in s3fb_ddc_read() argument
194 if (s3fb_ddc_needs_mmio(par->chip)) in s3fb_ddc_read()
195 return readb(par->mmio + DDC_MMIO_REG); in s3fb_ddc_read()
197 return vga_rcrt(par->state.vgabase, DDC_REG); in s3fb_ddc_read()
200 static void s3fb_ddc_write(struct s3fb_info *par, u8 val) in s3fb_ddc_write() argument
202 if (s3fb_ddc_needs_mmio(par->chip)) in s3fb_ddc_write()
203 writeb(val, par->mmio + DDC_MMIO_REG); in s3fb_ddc_write()
205 vga_wcrt(par->state.vgabase, DDC_REG, val); in s3fb_ddc_write()
210 struct s3fb_info *par = data; in s3fb_ddc_setscl() local
213 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; in s3fb_ddc_setscl()
[all …]
Dtridentfb.c41 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
43 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
45 (struct tridentfb_par *par, const char*,
175 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v) in writemmr() argument
177 fb_writel(v, par->io_virt + r); in writemmr()
180 static inline u32 readmmr(struct tridentfb_par *par, u16 r) in readmmr() argument
182 return fb_readl(par->io_virt + r); in readmmr()
193 struct tridentfb_par *par = data; in tridentfb_ddc_setscl_tgui() local
194 u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI; in tridentfb_ddc_setscl_tgui()
201 vga_mm_wcrt(par->io_virt, I2C, reg); in tridentfb_ddc_setscl_tgui()
[all …]
/linux-6.12.1/drivers/video/fbdev/geode/
Dsuspend_gx.c14 static void gx_save_regs(struct gxfb_par *par) in gx_save_regs() argument
20 i = read_gp(par, GP_BLT_STATUS); in gx_save_regs()
24 rdmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel); in gx_save_regs()
25 rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll); in gx_save_regs()
27 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); in gx_save_regs()
30 memcpy(par->gp, par->gp_regs, sizeof(par->gp)); in gx_save_regs()
31 memcpy(par->dc, par->dc_regs, sizeof(par->dc)); in gx_save_regs()
32 memcpy(par->vp, par->vid_regs, sizeof(par->vp)); in gx_save_regs()
33 memcpy(par->fp, par->vid_regs + VP_FP_START, sizeof(par->fp)); in gx_save_regs()
36 write_dc(par, DC_PAL_ADDRESS, 0); in gx_save_regs()
[all …]
Dlxfb_ops.c182 struct lxfb_par *par = info->par; in lx_graphics_disable() local
187 write_vp(par, VP_A1T, 0); in lx_graphics_disable()
188 write_vp(par, VP_A2T, 0); in lx_graphics_disable()
189 write_vp(par, VP_A3T, 0); in lx_graphics_disable()
192 val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GENERAL_CFG_VGAE | in lx_graphics_disable()
195 write_dc(par, DC_GENERAL_CFG, val); in lx_graphics_disable()
197 val = read_vp(par, VP_VCFG) & ~VP_VCFG_VID_EN; in lx_graphics_disable()
198 write_vp(par, VP_VCFG, val); in lx_graphics_disable()
200 write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK | in lx_graphics_disable()
203 val = read_dc(par, DC_GENLK_CTL) & ~DC_GENLK_CTL_GENLK_EN; in lx_graphics_disable()
[all …]
/linux-6.12.1/drivers/video/fbdev/riva/
Dnv_driver.c46 static inline unsigned char MISCin(struct riva_par *par) in MISCin() argument
48 return (VGA_RD08(par->riva.PVIO, 0x3cc)); in MISCin()
52 riva_is_connected(struct riva_par *par, Bool second) in riva_is_connected() argument
54 volatile U032 __iomem *PRAMDAC = par->riva.PRAMDAC0; in riva_is_connected()
69 NV_WR32(par->riva.PRAMDAC0, 0x0610, 0x94050140); in riva_is_connected()
70 NV_WR32(par->riva.PRAMDAC0, 0x0608, 0x00001000); in riva_is_connected()
76 NV_WR32(par->riva.PRAMDAC0, 0x0608, in riva_is_connected()
77 NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF); in riva_is_connected()
86 riva_override_CRTC(struct riva_par *par) in riva_override_CRTC() argument
90 par->SecondCRTC ? 1 : 0); in riva_override_CRTC()
[all …]
/linux-6.12.1/drivers/video/fbdev/aty/
Dmach64_accel.c40 void aty_reset_engine(struct atyfb_par *par) in aty_reset_engine() argument
44 aty_ld_le32(GEN_TEST_CNTL, par) & in aty_reset_engine()
45 ~(GUI_ENGINE_ENABLE | HWCURSOR_ENABLE), par); in aty_reset_engine()
48 aty_ld_le32(GEN_TEST_CNTL, par) | GUI_ENGINE_ENABLE, par); in aty_reset_engine()
52 aty_ld_le32(BUS_CNTL, par) | BUS_HOST_ERR_ACK | BUS_FIFO_ERR_ACK, par); in aty_reset_engine()
54 par->fifo_space = 0; in aty_reset_engine()
57 static void reset_GTC_3D_engine(const struct atyfb_par *par) in reset_GTC_3D_engine() argument
59 aty_st_le32(SCALE_3D_CNTL, 0xc0, par); in reset_GTC_3D_engine()
61 aty_st_le32(SETUP_CNTL, 0x00, par); in reset_GTC_3D_engine()
63 aty_st_le32(SCALE_3D_CNTL, 0x00, par); in reset_GTC_3D_engine()
[all …]
Datyfb_base.c149 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par) in aty_st_lcd() argument
152 aty_st_le32(lt_lcd_regs[index], val, par); in aty_st_lcd()
157 temp = aty_ld_le32(LCD_INDEX, par); in aty_st_lcd()
158 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par); in aty_st_lcd()
160 aty_st_le32(LCD_DATA, val, par); in aty_st_lcd()
164 u32 aty_ld_lcd(int index, const struct atyfb_par *par) in aty_ld_lcd() argument
167 return aty_ld_le32(lt_lcd_regs[index], par); in aty_ld_lcd()
172 temp = aty_ld_le32(LCD_INDEX, par); in aty_ld_lcd()
173 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par); in aty_ld_lcd()
175 return aty_ld_le32(LCD_DATA, par); in aty_ld_lcd()
[all …]

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