Searched refs:num_tx_sched_layers (Results 1 – 5 of 5) sorted by relevance
764 for (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) { in ice_sched_clear_rl_prof()863 hw->num_tx_sched_layers = 0; in ice_sched_cleanup_all()1112 return hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET; in ice_sched_get_qgrp_layer()1129 if (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS) in ice_sched_get_vsi_layer()1130 return hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET; in ice_sched_get_vsi_layer()1131 else if (hw->num_tx_sched_layers == ICE_SCHED_5_LAYERS) in ice_sched_get_vsi_layer()1133 return hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET; in ice_sched_get_vsi_layer()1150 if (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS) in ice_sched_get_agg_layer()1151 return hw->num_tx_sched_layers - ICE_AGG_LAYER_OFFSET; in ice_sched_get_agg_layer()1341 hw->num_tx_sched_layers = le16_to_cpu(buf->sched_props.logical_levels); in ice_sched_query_res_alloc()[all …]
2391 hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS) { in ice_cfg_tx_topo()2398 hw->num_tx_sched_layers == ICE_SCHED_5_LAYERS) { in ice_cfg_tx_topo()2413 hw->num_tx_sched_layers == ICE_SCHED_5_LAYERS) { in ice_cfg_tx_topo()
914 u8 num_tx_sched_layers; member
4519 u8 num_tx_sched_layers = hw->num_tx_sched_layers; in ice_init_tx_topology() local4527 if (hw->num_tx_sched_layers > num_tx_sched_layers) in ice_init_tx_topology()
4847 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); in ice_ena_vsi_txq()5076 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, in ice_ena_vsi_rdma_qset()