Searched refs:num_memclk_levels (Results 1 – 13 of 13) sorted by relevance
1038 &num_entries_per_clk->num_memclk_levels); in dcn32_get_memclk_states_from_smu()1043 …num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_… in dcn32_get_memclk_states_from_smu()1050 if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) { in dcn32_get_memclk_states_from_smu()1051 num_levels = num_entries_per_clk->num_memclk_levels; in dcn32_get_memclk_states_from_smu()1056 … clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz; in dcn32_get_memclk_states_from_smu()
184 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = in dcn401_update_bw_bounding_box_fpu()185 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; in dcn401_update_bw_bounding_box_fpu()211 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) { in dcn401_update_bw_bounding_box_fpu()
86 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_memclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()715 …able.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_… in dcn401_update_clocks_legacy()1521 &num_entries_per_clk->num_memclk_levels); in dcn401_get_memclk_states_from_smu()1522 if (num_entries_per_clk->num_memclk_levels) { in dcn401_get_memclk_states_from_smu()1524 … clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz; in dcn401_get_memclk_states_from_smu()1528 if (num_entries_per_clk->num_memclk_levels && clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz == in dcn401_get_memclk_states_from_smu()1529 … clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz) in dcn401_get_memclk_states_from_smu()1541 if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) { in dcn401_get_memclk_states_from_smu()1542 num_levels = num_entries_per_clk->num_memclk_levels; in dcn401_get_memclk_states_from_smu()
403 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = num_uclk_dpms; in build_synthetic_soc_states()875 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = in dcn321_update_bw_bounding_box_fpu()876 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; in dcn321_update_bw_bounding_box_fpu()903 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) { in dcn321_update_bw_bounding_box_fpu()
167 unsigned int num_memclk_levels; member
532 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels; i++)… in dml2_init_soc_states()
121 unsigned int num_memclk_levels; member
382 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = in dcn35_update_bw_bounding_box_fpu()
416 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = in dcn351_update_bw_bounding_box_fpu()
2511 …ram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1; in dcn32_calculate_wm_and_dlg_fpu()2855 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = num_uclk_dpms; in build_synthetic_soc_states()3320 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = in dcn32_update_bw_bounding_box_fpu()3321 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; in dcn32_update_bw_bounding_box_fpu()3347 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) { in dcn32_update_bw_bounding_box_fpu()3599 int num_mclk_levels = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; in dcn32_override_min_req_memclk()
153 if (dc_clk_table->num_entries_per_clk.num_memclk_levels) { in dml21_apply_soc_bb_overrides()154 dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; in dml21_apply_soc_bb_overrides()
904 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
235 …(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels && dc->clk_mgr->bw_params… in dcn401_init_hw()