/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
D | pppcielanes.c | 56 uint8_t encode_pcie_lane_width(uint32_t num_lanes) in encode_pcie_lane_width() argument 58 return pp_r600_encode_lanes[num_lanes]; in encode_pcie_lane_width() 61 uint8_t decode_pcie_lane_width(uint32_t num_lanes) in decode_pcie_lane_width() argument 63 return pp_r600_decoded_lanes[num_lanes]; in decode_pcie_lane_width()
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D | pppcielanes.h | 27 extern uint8_t encode_pcie_lane_width(uint32_t num_lanes); 28 extern uint8_t decode_pcie_lane_width(uint32_t num_lanes);
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/linux-6.12.1/drivers/media/i2c/adv748x/ |
D | adv748x-core.c | 367 tx->active_lanes = min(tx->num_lanes, 2U); in adv748x_link_setup() 380 tx->active_lanes = tx->num_lanes; in adv748x_link_setup() 613 unsigned int num_lanes; in adv748x_parse_csi2_lanes() local 623 num_lanes = vep.bus.mipi_csi2.num_data_lanes; in adv748x_parse_csi2_lanes() 626 if (num_lanes != 1 && num_lanes != 2 && num_lanes != 4) { in adv748x_parse_csi2_lanes() 628 num_lanes); in adv748x_parse_csi2_lanes() 632 state->txa.num_lanes = num_lanes; in adv748x_parse_csi2_lanes() 633 state->txa.active_lanes = num_lanes; in adv748x_parse_csi2_lanes() 634 adv_dbg(state, "TXA: using %u lanes\n", state->txa.num_lanes); in adv748x_parse_csi2_lanes() 638 if (num_lanes != 1) { in adv748x_parse_csi2_lanes() [all …]
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/linux-6.12.1/drivers/phy/rockchip/ |
D | phy-rockchip-snps-pcie3.c | 67 int num_lanes; member 106 for (int i = 0; i < priv->num_lanes; i++) { in rockchip_p3phy_rk3568_init() 164 for (int i = 0; i < priv->num_lanes; i++) { in rockchip_p3phy_rk3588_init() 284 priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes", in rockchip_p3phy_probe() 289 if (priv->num_lanes == -EINVAL) { in rockchip_p3phy_probe() 291 priv->num_lanes = 1; in rockchip_p3phy_probe() 293 } else if (priv->num_lanes < 0) { in rockchip_p3phy_probe() 294 dev_err(dev, "failed to read data-lanes property %d\n", priv->num_lanes); in rockchip_p3phy_probe() 295 return priv->num_lanes; in rockchip_p3phy_probe()
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D | phy-rockchip-usbdp.c | 879 int ret, i, num_lanes; in rk_udphy_parse_lane_mux_data() local 881 num_lanes = device_property_count_u32(udphy->dev, "rockchip,dp-lane-mux"); in rk_udphy_parse_lane_mux_data() 882 if (num_lanes < 0) { in rk_udphy_parse_lane_mux_data() 888 if (num_lanes != 2 && num_lanes != 4) in rk_udphy_parse_lane_mux_data() 893 udphy->dp_lane_sel, num_lanes); in rk_udphy_parse_lane_mux_data() 897 for (i = 0; i < num_lanes; i++) { in rk_udphy_parse_lane_mux_data() 906 for (j = i + 1; j < num_lanes; j++) { in rk_udphy_parse_lane_mux_data() 914 if (num_lanes == 2) { in rk_udphy_parse_lane_mux_data()
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/linux-6.12.1/drivers/pci/controller/dwc/ |
D | pci-keystone.c | 128 int num_lanes; member 979 int num_lanes = ks_pcie->num_lanes; in ks_pcie_disable_phy() local 981 while (num_lanes--) { in ks_pcie_disable_phy() 982 phy_power_off(ks_pcie->phy[num_lanes]); in ks_pcie_disable_phy() 983 phy_exit(ks_pcie->phy[num_lanes]); in ks_pcie_disable_phy() 991 int num_lanes = ks_pcie->num_lanes; in ks_pcie_enable_phy() local 993 for (i = 0; i < num_lanes; i++) { in ks_pcie_enable_phy() 1144 u32 num_lanes; in ks_pcie_probe() local 1201 ret = of_property_read_u32(np, "num-lanes", &num_lanes); in ks_pcie_probe() 1203 num_lanes = 1; in ks_pcie_probe() [all …]
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/linux-6.12.1/drivers/phy/ti/ |
D | phy-j721e-wiz.c | 385 u32 num_lanes; member 417 u32 num_lanes = wiz->num_lanes; in wiz_p_mac_div_sel() local 421 for (i = 0; i < num_lanes; i++) { in wiz_p_mac_div_sel() 440 u32 num_lanes = wiz->num_lanes; in wiz_mode_select() local 445 for (i = 0; i < num_lanes; i++) { in wiz_mode_select() 469 u32 num_lanes = wiz->num_lanes; in wiz_init_raw_interface() local 473 for (i = 0; i < num_lanes; i++) { in wiz_init_raw_interface() 522 int num_lanes = wiz->num_lanes; in wiz_regfield_init() local 611 for (i = 0; i < num_lanes; i++) { in wiz_regfield_init() 1276 u32 num_lanes = wiz->num_lanes; in wiz_phy_reset_deassert() local [all …]
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/linux-6.12.1/drivers/acpi/ |
D | mipi-disco-img.c | 492 int num_lanes = 0; in init_csi2_port() local 509 num_lanes = ret; in init_csi2_port() 511 if (num_lanes > ACPI_DEVICE_CSI2_DATA_LANES) { in init_csi2_port() 513 num_lanes); in init_csi2_port() 514 num_lanes = ACPI_DEVICE_CSI2_DATA_LANES; in init_csi2_port() 519 val, num_lanes); in init_csi2_port() 523 for (i = 0; i < num_lanes; i++) in init_csi2_port() 529 num_lanes); in init_csi2_port() 536 } else if (ret * BITS_PER_TYPE(u8) < num_lanes + 1) { in init_csi2_port() 538 ret * BITS_PER_TYPE(u8), num_lanes + 1); in init_csi2_port() [all …]
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/linux-6.12.1/drivers/phy/mediatek/ |
D | phy-mtk-pcie.c | 55 int num_lanes; member 122 for (i = 0; i < pcie_phy->data->num_lanes; i++) in mtk_pcie_phy_init() 184 pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes * in mtk_pcie_read_efuse() 189 for (i = 0; i < pcie_phy->data->num_lanes; i++) { in mtk_pcie_read_efuse() 245 .num_lanes = 2,
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D | phy-mtk-mipi-csi-0-5.c | 30 u32 num_lanes; member 184 if (priv->num_lanes != 4) { in mtk_mipi_cdphy_xlate() 231 ret = of_property_read_u32(dev->of_node, "num-lanes", &port->num_lanes); in mtk_mipi_cdphy_probe()
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/linux-6.12.1/drivers/gpu/drm/bridge/adv7511/ |
D | adv7533.c | 171 u32 num_lanes; in adv7533_parse_dt() local 173 of_property_read_u32(np, "adi,dsi-lanes", &num_lanes); in adv7533_parse_dt() 175 if (num_lanes < 1 || num_lanes > 4) in adv7533_parse_dt() 178 adv->num_dsi_lanes = num_lanes; in adv7533_parse_dt()
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/linux-6.12.1/drivers/nvdimm/ |
D | region.c | 24 if (nd_region->num_lanes > num_online_cpus() in nd_region_probe() 25 && nd_region->num_lanes < num_possible_cpus() in nd_region_probe() 28 num_online_cpus(), nd_region->num_lanes, in nd_region_probe() 31 nd_region->num_lanes); in nd_region_probe()
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/linux-6.12.1/drivers/gpu/drm/bridge/cadence/ |
D | cdns-mhdp8546-core.c | 633 values[1] = link->num_lanes; in cdns_mhdp_link_configure() 896 CDNS_DP_LANE_EN_LANES(mhdp->link.num_lanes)); in cdns_mhdp_link_training_init() 900 phy_cfg.dp.lanes = mhdp->link.num_lanes; in cdns_mhdp_link_training_init() 941 for (i = 0; i < mhdp->link.num_lanes; i++) { in cdns_mhdp_get_adjust_train() 1006 for (i = 0; i < mhdp->link.num_lanes; i++) { in cdns_mhdp_adjust_requested_eq() 1029 for (i = 0; i < mhdp->link.num_lanes; i++) { in cdns_mhdp_print_lt_status() 1039 mhdp->link.num_lanes, mhdp->link.rate / 100, in cdns_mhdp_print_lt_status() 1072 phy_cfg.dp.lanes = mhdp->link.num_lanes; in cdns_mhdp_link_training_channel_eq() 1084 cdns_mhdp_adjust_lt(mhdp, mhdp->link.num_lanes, in cdns_mhdp_link_training_channel_eq() 1087 r = drm_dp_clock_recovery_ok(link_status, mhdp->link.num_lanes); in cdns_mhdp_link_training_channel_eq() [all …]
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/linux-6.12.1/drivers/media/platform/cadence/ |
D | cdns-csi2rx.c | 94 u8 num_lanes; member 185 fmt->bpp, 2 * csi2rx->num_lanes); in csi2rx_configure_ext_dphy() 190 csi2rx->num_lanes, cfg); in csi2rx_configure_ext_dphy() 221 reg = csi2rx->num_lanes << 8; in csi2rx_start() 222 for (i = 0; i < csi2rx->num_lanes; i++) { in csi2rx_start() 233 for (i = csi2rx->num_lanes; i < csi2rx->max_lanes; i++) { in csi2rx_start() 245 for (i = 0; i < csi2rx->num_lanes; i++) { in csi2rx_start() 637 csi2rx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; in csi2rx_parse_dt() 638 if (csi2rx->num_lanes > csi2rx->max_lanes) { in csi2rx_parse_dt() 640 csi2rx->num_lanes); in csi2rx_parse_dt() [all …]
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D | cdns-csi2tx.c | 116 unsigned int num_lanes; member 251 for (i = 0; i < csi2tx->num_lanes; i++) in csi2tx_dphy_init_finish() 273 for (i = 0; i < csi2tx->num_lanes; i++) in csi2tx_dphy_setup() 519 csi2tx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; in csi2tx_check_lanes() 520 if (csi2tx->num_lanes > csi2tx->max_lanes) { in csi2tx_check_lanes() 527 for (i = 0; i < csi2tx->num_lanes; i++) { in csi2tx_check_lanes() 627 csi2tx->num_lanes, csi2tx->max_lanes, csi2tx->max_streams, in csi2tx_probe()
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/linux-6.12.1/drivers/gpu/drm/msm/dp/ |
D | dp_panel.c | 68 link_info->num_lanes = drm_dp_max_lane_count(dpcd); in dp_panel_read_dpcd() 71 if (link_info->num_lanes > dp_panel->max_dp_lanes) in dp_panel_read_dpcd() 72 link_info->num_lanes = dp_panel->max_dp_lanes; in dp_panel_read_dpcd() 80 drm_dbg_dp(panel->drm_dev, "lane_count=%d\n", link_info->num_lanes); in dp_panel_read_dpcd() 100 data_rate_khz = link_info->num_lanes * link_info->rate * 8; in dp_panel_get_supported_bpp() 136 !is_lane_count_valid(dp_panel->link_info.num_lanes) || in dp_panel_read_sink_caps() 139 dp_panel->link_info.num_lanes); in dp_panel_read_sink_caps()
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D | dp_ctrl.c | 109 values[1] = link->num_lanes; in dp_aux_link_configure() 158 config |= ((ctrl->link->link_params.num_lanes - 1) in dp_ctrl_config_ctrl() 971 in.nlanes = ctrl->link->link_params.num_lanes; in dp_ctrl_calc_tu_parameters() 1071 lane_cnt = ctrl->link->link_params.num_lanes; in dp_ctrl_update_vx_px() 1148 ctrl->link->link_params.num_lanes)) { in dp_ctrl_link_train_1() 1204 if (ctrl->link->link_params.num_lanes == 1) in dp_ctrl_link_lane_down_shift() 1207 ctrl->link->link_params.num_lanes /= 2; in dp_ctrl_link_lane_down_shift() 1260 ctrl->link->link_params.num_lanes)) { in dp_ctrl_link_train_2() 1285 link_info.num_lanes = ctrl->link->link_params.num_lanes; in dp_ctrl_link_train() 1450 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; in dp_ctrl_enable_mainlink_clocks() [all …]
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/linux-6.12.1/drivers/pci/controller/cadence/ |
D | pci-j721e.c | 58 u32 num_lanes; member 213 u32 lanes = pcie->num_lanes; in j721e_pcie_set_lane_count() 438 u32 num_lanes; in j721e_pcie_probe() local 507 ret = of_property_read_u32(node, "num-lanes", &num_lanes); in j721e_pcie_probe() 508 if (ret || num_lanes > data->max_lanes) { in j721e_pcie_probe() 510 num_lanes = 1; in j721e_pcie_probe() 513 pcie->num_lanes = num_lanes; in j721e_pcie_probe()
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/linux-6.12.1/drivers/media/i2c/ |
D | ov8858.c | 122 unsigned int num_lanes; member 1341 reg_list = ov8858->num_lanes == 4 in ov8858_start_stream() 1724 pixel_rate = OV8858_LINK_FREQ * 2 * ov8858->num_lanes / 10; in ov8858_init_ctrls() 1809 ov8858->global_regs = ov8858->num_lanes == 4 in ov8858_check_sensor_id() 1812 } else if (ov8858->num_lanes == 2) { in ov8858_check_sensor_id() 1862 ov8858->num_lanes = vep.bus.mipi_csi2.num_data_lanes; in ov8858_parse_of() 1863 switch (ov8858->num_lanes) { in ov8858_parse_of() 1869 ov8858->num_lanes); in ov8858_parse_of()
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/linux-6.12.1/drivers/gpu/drm/bridge/ |
D | sii902x.c | 851 int num_lanes, i; in sii902x_audio_codec_init() local 859 num_lanes = of_property_read_variable_u8_array(dev->of_node, in sii902x_audio_codec_init() 864 if (num_lanes == -EINVAL) { in sii902x_audio_codec_init() 868 num_lanes = 1; in sii902x_audio_codec_init() 870 } else if (num_lanes < 0) { in sii902x_audio_codec_init() 873 __func__, num_lanes); in sii902x_audio_codec_init() 874 return num_lanes; in sii902x_audio_codec_init() 876 codec_data.max_i2s_channels = 2 * num_lanes; in sii902x_audio_codec_init() 878 for (i = 0; i < num_lanes; i++) in sii902x_audio_codec_init()
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D | tc358767.c | 353 u8 num_lanes; member 566 if (tc->link.num_lanes == 2) in tc_srcctrl() 829 u8 revision, num_lanes; in tc_get_display_props() local 842 num_lanes = drm_dp_max_lane_count(tc->link.dpcd); in tc_get_display_props() 851 if (num_lanes > 2) { in tc_get_display_props() 853 num_lanes = 2; in tc_get_display_props() 856 tc->link.num_lanes = num_lanes; in tc_get_display_props() 877 tc->link.num_lanes, in tc_get_display_props() 1001 out_bw = tc->link.num_lanes * tc->link.rate; in tc_set_edp_video_mode() 1120 if (tc->link.num_lanes == 2) in tc_main_link_enable() [all …]
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/linux-6.12.1/drivers/media/platform/samsung/exynos4-is/ |
D | mipi-csis.c | 216 u32 num_lanes; member 322 mask = (1 << (state->num_lanes + 1)) - 1; in s5pcsis_system_enable() 360 val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (state->num_lanes - 1); in s5pcsis_set_params() 754 state->num_lanes = endpoint.bus.mipi_csi2.num_data_lanes; in s5pcsis_parse_dt() 792 if (state->num_lanes == 0 || state->num_lanes > state->max_num_lanes) { in s5pcsis_probe() 794 state->num_lanes, state->max_num_lanes); in s5pcsis_probe() 875 state->num_lanes, state->hs_settle, state->wclk_ext, in s5pcsis_probe()
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/linux-6.12.1/drivers/phy/cadence/ |
D | phy-cadence-torrent.c | 344 u32 num_lanes; member 1105 pll_bits = ((1 << inst->num_lanes) - 1); in cdns_torrent_dp_set_pll_en() 1124 u32 num_lanes, in cdns_torrent_dp_set_power_state() argument 1150 for (i = 0; i < num_lanes; i++) { in cdns_torrent_dp_set_power_state() 1171 struct cdns_torrent_inst *inst, u32 num_lanes) in cdns_torrent_dp_run() argument 1192 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes, in cdns_torrent_dp_run() 1197 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes, in cdns_torrent_dp_run() 1222 u32 rate, u32 num_lanes) in cdns_torrent_dp_pma_cmn_rate() argument 1263 for (i = 0; i < num_lanes; i++) in cdns_torrent_dp_pma_cmn_rate() 1394 if (dp->lanes > inst->num_lanes) in cdns_torrent_dp_verify_config() [all …]
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/linux-6.12.1/drivers/gpu/drm/xlnx/ |
D | zynqmp_dp.c | 319 u8 num_lanes; member 391 for (i = 0; i < dp->num_lanes; i++) { in zynqmp_dp_phy_init() 405 for (i = dp->num_lanes - 1; i >= 0; i--) { in zynqmp_dp_phy_init() 427 for (i = 0; i < dp->num_lanes; i++) { in zynqmp_dp_phy_exit() 434 for (i = 0; i < dp->num_lanes; i++) { in zynqmp_dp_phy_exit() 469 if (dp->num_lanes) in zynqmp_dp_phy_probe() 486 dp->num_lanes++; in zynqmp_dp_phy_probe() 505 ready = (1 << dp->num_lanes) - 1; in zynqmp_dp_phy_ready() 1560 dp->num_lanes); in zynqmp_dp_bridge_detect() 1814 dp->num_lanes); in zynqmp_dp_probe()
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/linux-6.12.1/drivers/staging/media/atomisp/pci/ |
D | ia_css_input_port.h | 55 unsigned int num_lanes; /** Number of lanes used (4-lane port only) */ member
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