Searched refs:num_dispclk_levels (Results 1 – 13 of 13) sorted by relevance
193 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn401_update_bw_bounding_box_fpu()194 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; in dcn401_update_bw_bounding_box_fpu()229 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) { in dcn401_update_bw_bounding_box_fpu()
170 unsigned int num_dispclk_levels; member
548 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels; i++… in dml2_init_soc_states()
94 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()268 &num_entries_per_clk->num_dispclk_levels); in dcn401_init_clocks()270 …if (num_entries_per_clk->num_dispclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz … in dcn401_init_clocks()271 …clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dispclk_levels - 1].dispclk_mh… in dcn401_init_clocks()281 num_entries_per_clk->num_dispclk_levels) in dcn401_init_clocks()285 for (i = 0; i < num_entries_per_clk->num_dispclk_levels; i++) in dcn401_init_clocks()
124 unsigned int num_dispclk_levels; member
884 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn321_update_bw_bounding_box_fpu()885 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; in dcn321_update_bw_bounding_box_fpu()921 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) { in dcn321_update_bw_bounding_box_fpu()
214 &num_entries_per_clk->num_dispclk_levels); in dcn32_init_clocks()215 num_levels = num_entries_per_clk->num_dispclk_levels; in dcn32_init_clocks()233 num_entries_per_clk->num_dispclk_levels) in dcn32_init_clocks()
376 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn35_update_bw_bounding_box_fpu()
410 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn351_update_bw_bounding_box_fpu()
176 if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) { in dml21_apply_soc_bb_overrides()177 dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels; in dml21_apply_soc_bb_overrides()
3329 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn32_update_bw_bounding_box_fpu()3330 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; in dcn32_update_bw_bounding_box_fpu()3365 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) { in dcn32_update_bw_bounding_box_fpu()
901 bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
232 …(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels && dc->clk_mgr->bw_param… in dcn401_init_hw()