Searched refs:num_dcfclk_levels (Results 1 – 13 of 13) sorted by relevance
178 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn401_update_bw_bounding_box_fpu()179 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; in dcn401_update_bw_bounding_box_fpu()199 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; i++) { in dcn401_update_bw_bounding_box_fpu()
165 unsigned int num_dcfclk_levels; member
519 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++)… in dml2_init_soc_states()
119 unsigned int num_dcfclk_levels; member
105 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()239 &num_entries_per_clk->num_dcfclk_levels); in dcn401_init_clocks()241 if (num_entries_per_clk->num_dcfclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz == in dcn401_init_clocks()242 … clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dcfclk_levels - 1].dcfclk_mhz) in dcn401_init_clocks()279 if (num_entries_per_clk->num_dcfclk_levels && in dcn401_init_clocks()
869 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn321_update_bw_bounding_box_fpu()870 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; in dcn321_update_bw_bounding_box_fpu()891 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; i++) { in dcn321_update_bw_bounding_box_fpu()
193 &num_entries_per_clk->num_dcfclk_levels); in dcn32_init_clocks()231 if (num_entries_per_clk->num_dcfclk_levels && in dcn32_init_clocks()
372 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn35_update_bw_bounding_box_fpu()
406 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn351_update_bw_bounding_box_fpu()
107 if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { in dml21_apply_soc_bb_overrides()108 dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; in dml21_apply_soc_bb_overrides()
3314 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn32_update_bw_bounding_box_fpu()3315 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; in dcn32_update_bw_bounding_box_fpu()3335 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; i++) { in dcn32_update_bw_bounding_box_fpu()
900 bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = clock_table->NumDcfClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
231 …(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels && dc->clk_mgr->bw_params… in dcn401_init_hw()