Home
last modified time | relevance | path

Searched refs:nitrox_write_csr (Results 1 – 5 of 5) sorted by relevance

/linux-6.12.1/drivers/crypto/cavium/nitrox/
Dnitrox_hal.c31 nitrox_write_csr(ndev, EMU_AE_ENABLEX(i), emu_ae.value); in emu_enable_cores()
32 nitrox_write_csr(ndev, EMU_SE_ENABLEX(i), emu_se.value); in emu_enable_cores()
59 nitrox_write_csr(ndev, offset, emu_wd_int.value); in nitrox_config_emu_unit()
61 nitrox_write_csr(ndev, offset, emu_ge_int.value); in nitrox_config_emu_unit()
76 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in reset_pkt_input_ring()
90 nitrox_write_csr(ndev, offset, pkt_in_cnts.value); in reset_pkt_input_ring()
105 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in enable_pkt_input_ring()
138 nitrox_write_csr(ndev, offset, cmdq->dma); in nitrox_config_pkt_input_rings()
144 nitrox_write_csr(ndev, offset, pkt_in_rsize.value); in nitrox_config_pkt_input_rings()
148 nitrox_write_csr(ndev, offset, 0xffffffff); in nitrox_config_pkt_input_rings()
[all …]
Dnitrox_isr.c48 nitrox_write_csr(ndev, NPS_CORE_INT, value); in clear_nps_core_err_intr()
66 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
72 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
82 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
90 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
95 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
105 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
116 nitrox_write_csr(ndev, POM_INT, value); in clear_pom_err_intr()
125 nitrox_write_csr(ndev, PEM0_INT, value); in clear_pem_err_intr()
142 nitrox_write_csr(ndev, offset, value); in clear_lbc_err_intr()
[all …]
Dnitrox_main.c94 nitrox_write_csr(ndev, offset, block_num); in write_to_ucd_unit()
101 nitrox_write_csr(ndev, offset, data); in write_to_ucd_unit()
153 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_load_fw()
169 nitrox_write_csr(ndev, offset, core_2_eid_val.value); in nitrox_load_fw()
205 nitrox_write_csr(ndev, offset, aqm_grp_execmask_lo.value); in nitrox_load_fw()
208 nitrox_write_csr(ndev, offset, aqm_grp_execmask_hi.value); in nitrox_load_fw()
224 nitrox_write_csr(ndev, offset, core_2_eid_val.value); in nitrox_load_fw()
Dnitrox_mbx.c53 nitrox_write_csr(ndev, reg_addr, value); in pf2vf_write_mbox()
151 nitrox_write_csr(ndev, reg_addr, BIT_ULL(i)); in nitrox_pf2vf_mbox_handler()
175 nitrox_write_csr(ndev, reg_addr, BIT_ULL(i)); in nitrox_pf2vf_mbox_handler()
Dnitrox_dev.h286 static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset, in nitrox_write_csr() function