1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Comedi driver for NI PCI-MIO E series cards
4 *
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
7 */
8
9 /*
10 * Driver: ni_pcimio
11 * Description: National Instruments PCI-MIO-E series and M series (all boards)
12 * Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
13 * Herman Bruyninckx, Terry Barnaby
14 * Status: works
15 * Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
16 * PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014,
17 * PCI-6040E, PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E,
18 * PCI-6071E, PCI-6023E, PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E,
19 * PCI-6035E, PCI-6052E, PCI-6110, PCI-6111, PCI-6220, PXI-6220,
20 * PCI-6221, PXI-6221, PCI-6224, PXI-6224, PCI-6225, PXI-6225,
21 * PCI-6229, PXI-6229, PCI-6250, PXI-6250, PCI-6251, PXI-6251,
22 * PCIe-6251, PXIe-6251, PCI-6254, PXI-6254, PCI-6259, PXI-6259,
23 * PCIe-6259, PXIe-6259, PCI-6280, PXI-6280, PCI-6281, PXI-6281,
24 * PCI-6284, PXI-6284, PCI-6289, PXI-6289, PCI-6711, PXI-6711,
25 * PCI-6713, PXI-6713, PXI-6071E, PCI-6070E, PXI-6070E,
26 * PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
27 * PCI-6143, PXI-6143
28 * Updated: Mon, 16 Jan 2017 12:56:04 +0000
29 *
30 * These boards are almost identical to the AT-MIO E series, except that
31 * they use the PCI bus instead of ISA (i.e., AT). See the notes for the
32 * ni_atmio.o driver for additional information about these boards.
33 *
34 * Autocalibration is supported on many of the devices, using the
35 * comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
36 * M-Series boards do analog input and analog output calibration entirely
37 * in software. The software calibration corrects the analog input for
38 * offset, gain and nonlinearity. The analog outputs are corrected for
39 * offset and gain. See the comedilib documentation on
40 * comedi_get_softcal_converter() for more information.
41 *
42 * By default, the driver uses DMA to transfer analog input data to
43 * memory. When DMA is enabled, not all triggering features are
44 * supported.
45 *
46 * Digital I/O may not work on 673x.
47 *
48 * Note that the PCI-6143 is a simultaineous sampling device with 8
49 * convertors. With this board all of the convertors perform one
50 * simultaineous sample during a scan interval. The period for a scan
51 * is used for the convert time in a Comedi cmd. The convert trigger
52 * source is normally set to TRIG_NOW by default.
53 *
54 * The RTSI trigger bus is supported on these cards on subdevice 10.
55 * See the comedilib documentation for details.
56 *
57 * Information (number of channels, bits, etc.) for some devices may be
58 * incorrect. Please check this and submit a bug if there are problems
59 * for your device.
60 *
61 * SCXI is probably broken for m-series boards.
62 *
63 * Bugs:
64 * - When DMA is enabled, COMEDI_EV_CONVERT does not work correctly.
65 */
66
67 /*
68 * The PCI-MIO E series driver was originally written by
69 * Tomasz Motylewski <...>, and ported to comedi by ds.
70 *
71 * References:
72 * 341079b.pdf PCI E Series Register-Level Programmer Manual
73 * 340934b.pdf DAQ-STC reference manual
74 *
75 * 322080b.pdf 6711/6713/6715 User Manual
76 *
77 * 320945c.pdf PCI E Series User Manual
78 * 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
79 *
80 * ISSUES:
81 * - need to deal with external reference for DAC, and other DAC
82 * properties in board properties
83 * - deal with at-mio-16de-10 revision D to N changes, etc.
84 * - need to add other CALDAC type
85 * - need to slow down DAC loading. I don't trust NI's claim that
86 * two writes to the PCI bus slows IO enough. I would prefer to
87 * use udelay().
88 * Timing specs: (clock)
89 * AD8522 30ns
90 * DAC8043 120ns
91 * DAC8800 60ns
92 * MB88341 ?
93 */
94
95 #include <linux/module.h>
96 #include <linux/delay.h>
97 #include <linux/comedi/comedi_pci.h>
98 #include <asm/byteorder.h>
99
100 #include "ni_stc.h"
101 #include "mite.h"
102
103 #define PCIDMA
104
105 static const struct comedi_lrange range_ni_E_ao_ext = {
106 4, {
107 BIP_RANGE(10),
108 UNI_RANGE(10),
109 RANGE_ext(-1, 1),
110 RANGE_ext(0, 1)
111 }
112 };
113
114 /*
115 * These are not all the possible ao ranges for 628x boards.
116 * They can do OFFSET +- REFERENCE where OFFSET can be
117 * 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
118 * be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
119 * 63 different possibilities. An AO channel
120 * can not act as it's own OFFSET or REFERENCE.
121 */
122 static const struct comedi_lrange range_ni_M_628x_ao = {
123 8, {
124 BIP_RANGE(10),
125 BIP_RANGE(5),
126 BIP_RANGE(2),
127 BIP_RANGE(1),
128 RANGE(-5, 15),
129 UNI_RANGE(10),
130 RANGE(3, 7),
131 RANGE(4, 6),
132 RANGE_ext(-1, 1)
133 }
134 };
135
136 static const struct comedi_lrange range_ni_M_625x_ao = {
137 3, {
138 BIP_RANGE(10),
139 BIP_RANGE(5),
140 RANGE_ext(-1, 1)
141 }
142 };
143
144 enum ni_pcimio_boardid {
145 BOARD_PCIMIO_16XE_50,
146 BOARD_PCIMIO_16XE_10,
147 BOARD_PCI6014,
148 BOARD_PXI6030E,
149 BOARD_PCIMIO_16E_1,
150 BOARD_PCIMIO_16E_4,
151 BOARD_PXI6040E,
152 BOARD_PCI6031E,
153 BOARD_PCI6032E,
154 BOARD_PCI6033E,
155 BOARD_PCI6071E,
156 BOARD_PCI6023E,
157 BOARD_PCI6024E,
158 BOARD_PCI6025E,
159 BOARD_PXI6025E,
160 BOARD_PCI6034E,
161 BOARD_PCI6035E,
162 BOARD_PCI6052E,
163 BOARD_PCI6110,
164 BOARD_PCI6111,
165 /* BOARD_PCI6115, */
166 /* BOARD_PXI6115, */
167 BOARD_PCI6711,
168 BOARD_PXI6711,
169 BOARD_PCI6713,
170 BOARD_PXI6713,
171 BOARD_PCI6731,
172 /* BOARD_PXI6731, */
173 BOARD_PCI6733,
174 BOARD_PXI6733,
175 BOARD_PXI6071E,
176 BOARD_PXI6070E,
177 BOARD_PXI6052E,
178 BOARD_PXI6031E,
179 BOARD_PCI6036E,
180 BOARD_PCI6220,
181 BOARD_PXI6220,
182 BOARD_PCI6221,
183 BOARD_PCI6221_37PIN,
184 BOARD_PXI6221,
185 BOARD_PCI6224,
186 BOARD_PXI6224,
187 BOARD_PCI6225,
188 BOARD_PXI6225,
189 BOARD_PCI6229,
190 BOARD_PXI6229,
191 BOARD_PCI6250,
192 BOARD_PXI6250,
193 BOARD_PCI6251,
194 BOARD_PXI6251,
195 BOARD_PCIE6251,
196 BOARD_PXIE6251,
197 BOARD_PCI6254,
198 BOARD_PXI6254,
199 BOARD_PCI6259,
200 BOARD_PXI6259,
201 BOARD_PCIE6259,
202 BOARD_PXIE6259,
203 BOARD_PCI6280,
204 BOARD_PXI6280,
205 BOARD_PCI6281,
206 BOARD_PXI6281,
207 BOARD_PCI6284,
208 BOARD_PXI6284,
209 BOARD_PCI6289,
210 BOARD_PXI6289,
211 BOARD_PCI6143,
212 BOARD_PXI6143,
213 };
214
215 static const struct ni_board_struct ni_boards[] = {
216 [BOARD_PCIMIO_16XE_50] = {
217 .name = "pci-mio-16xe-50",
218 .n_adchan = 16,
219 .ai_maxdata = 0xffff,
220 .ai_fifo_depth = 2048,
221 .alwaysdither = 1,
222 .gainlkup = ai_gain_8,
223 .ai_speed = 50000,
224 .n_aochan = 2,
225 .ao_maxdata = 0x0fff,
226 .ao_range_table = &range_bipolar10,
227 .ao_speed = 50000,
228 .caldac = { dac8800, dac8043 },
229 },
230 [BOARD_PCIMIO_16XE_10] = {
231 .name = "pci-mio-16xe-10", /* aka pci-6030E */
232 .n_adchan = 16,
233 .ai_maxdata = 0xffff,
234 .ai_fifo_depth = 512,
235 .alwaysdither = 1,
236 .gainlkup = ai_gain_14,
237 .ai_speed = 10000,
238 .n_aochan = 2,
239 .ao_maxdata = 0xffff,
240 .ao_fifo_depth = 2048,
241 .ao_range_table = &range_ni_E_ao_ext,
242 .ao_speed = 10000,
243 .caldac = { dac8800, dac8043, ad8522 },
244 },
245 [BOARD_PCI6014] = {
246 .name = "pci-6014",
247 .n_adchan = 16,
248 .ai_maxdata = 0xffff,
249 .ai_fifo_depth = 512,
250 .alwaysdither = 1,
251 .gainlkup = ai_gain_4,
252 .ai_speed = 5000,
253 .n_aochan = 2,
254 .ao_maxdata = 0xffff,
255 .ao_range_table = &range_bipolar10,
256 .ao_speed = 100000,
257 .caldac = { ad8804_debug },
258 },
259 [BOARD_PXI6030E] = {
260 .name = "pxi-6030e",
261 .n_adchan = 16,
262 .ai_maxdata = 0xffff,
263 .ai_fifo_depth = 512,
264 .alwaysdither = 1,
265 .gainlkup = ai_gain_14,
266 .ai_speed = 10000,
267 .n_aochan = 2,
268 .ao_maxdata = 0xffff,
269 .ao_fifo_depth = 2048,
270 .ao_range_table = &range_ni_E_ao_ext,
271 .ao_speed = 10000,
272 .caldac = { dac8800, dac8043, ad8522 },
273 },
274 [BOARD_PCIMIO_16E_1] = {
275 .name = "pci-mio-16e-1", /* aka pci-6070e */
276 .n_adchan = 16,
277 .ai_maxdata = 0x0fff,
278 .ai_fifo_depth = 512,
279 .gainlkup = ai_gain_16,
280 .ai_speed = 800,
281 .n_aochan = 2,
282 .ao_maxdata = 0x0fff,
283 .ao_fifo_depth = 2048,
284 .ao_range_table = &range_ni_E_ao_ext,
285 .ao_speed = 1000,
286 .caldac = { mb88341 },
287 },
288 [BOARD_PCIMIO_16E_4] = {
289 .name = "pci-mio-16e-4", /* aka pci-6040e */
290 .n_adchan = 16,
291 .ai_maxdata = 0x0fff,
292 .ai_fifo_depth = 512,
293 .gainlkup = ai_gain_16,
294 /*
295 * there have been reported problems with
296 * full speed on this board
297 */
298 .ai_speed = 2000,
299 .n_aochan = 2,
300 .ao_maxdata = 0x0fff,
301 .ao_fifo_depth = 512,
302 .ao_range_table = &range_ni_E_ao_ext,
303 .ao_speed = 1000,
304 .caldac = { ad8804_debug }, /* doc says mb88341 */
305 },
306 [BOARD_PXI6040E] = {
307 .name = "pxi-6040e",
308 .n_adchan = 16,
309 .ai_maxdata = 0x0fff,
310 .ai_fifo_depth = 512,
311 .gainlkup = ai_gain_16,
312 .ai_speed = 2000,
313 .n_aochan = 2,
314 .ao_maxdata = 0x0fff,
315 .ao_fifo_depth = 512,
316 .ao_range_table = &range_ni_E_ao_ext,
317 .ao_speed = 1000,
318 .caldac = { mb88341 },
319 },
320 [BOARD_PCI6031E] = {
321 .name = "pci-6031e",
322 .n_adchan = 64,
323 .ai_maxdata = 0xffff,
324 .ai_fifo_depth = 512,
325 .alwaysdither = 1,
326 .gainlkup = ai_gain_14,
327 .ai_speed = 10000,
328 .n_aochan = 2,
329 .ao_maxdata = 0xffff,
330 .ao_fifo_depth = 2048,
331 .ao_range_table = &range_ni_E_ao_ext,
332 .ao_speed = 10000,
333 .caldac = { dac8800, dac8043, ad8522 },
334 },
335 [BOARD_PCI6032E] = {
336 .name = "pci-6032e",
337 .n_adchan = 16,
338 .ai_maxdata = 0xffff,
339 .ai_fifo_depth = 512,
340 .alwaysdither = 1,
341 .gainlkup = ai_gain_14,
342 .ai_speed = 10000,
343 .caldac = { dac8800, dac8043, ad8522 },
344 },
345 [BOARD_PCI6033E] = {
346 .name = "pci-6033e",
347 .n_adchan = 64,
348 .ai_maxdata = 0xffff,
349 .ai_fifo_depth = 512,
350 .alwaysdither = 1,
351 .gainlkup = ai_gain_14,
352 .ai_speed = 10000,
353 .caldac = { dac8800, dac8043, ad8522 },
354 },
355 [BOARD_PCI6071E] = {
356 .name = "pci-6071e",
357 .n_adchan = 64,
358 .ai_maxdata = 0x0fff,
359 .ai_fifo_depth = 512,
360 .alwaysdither = 1,
361 .gainlkup = ai_gain_16,
362 .ai_speed = 800,
363 .n_aochan = 2,
364 .ao_maxdata = 0x0fff,
365 .ao_fifo_depth = 2048,
366 .ao_range_table = &range_ni_E_ao_ext,
367 .ao_speed = 1000,
368 .caldac = { ad8804_debug },
369 },
370 [BOARD_PCI6023E] = {
371 .name = "pci-6023e",
372 .n_adchan = 16,
373 .ai_maxdata = 0x0fff,
374 .ai_fifo_depth = 512,
375 .gainlkup = ai_gain_4,
376 .ai_speed = 5000,
377 .caldac = { ad8804_debug }, /* manual is wrong */
378 },
379 [BOARD_PCI6024E] = {
380 .name = "pci-6024e",
381 .n_adchan = 16,
382 .ai_maxdata = 0x0fff,
383 .ai_fifo_depth = 512,
384 .gainlkup = ai_gain_4,
385 .ai_speed = 5000,
386 .n_aochan = 2,
387 .ao_maxdata = 0x0fff,
388 .ao_range_table = &range_bipolar10,
389 .ao_speed = 100000,
390 .caldac = { ad8804_debug }, /* manual is wrong */
391 },
392 [BOARD_PCI6025E] = {
393 .name = "pci-6025e",
394 .n_adchan = 16,
395 .ai_maxdata = 0x0fff,
396 .ai_fifo_depth = 512,
397 .gainlkup = ai_gain_4,
398 .ai_speed = 5000,
399 .n_aochan = 2,
400 .ao_maxdata = 0x0fff,
401 .ao_range_table = &range_bipolar10,
402 .ao_speed = 100000,
403 .caldac = { ad8804_debug }, /* manual is wrong */
404 .has_8255 = 1,
405 },
406 [BOARD_PXI6025E] = {
407 .name = "pxi-6025e",
408 .n_adchan = 16,
409 .ai_maxdata = 0x0fff,
410 .ai_fifo_depth = 512,
411 .gainlkup = ai_gain_4,
412 .ai_speed = 5000,
413 .n_aochan = 2,
414 .ao_maxdata = 0x0fff,
415 .ao_range_table = &range_ni_E_ao_ext,
416 .ao_speed = 100000,
417 .caldac = { ad8804_debug }, /* manual is wrong */
418 .has_8255 = 1,
419 },
420 [BOARD_PCI6034E] = {
421 .name = "pci-6034e",
422 .n_adchan = 16,
423 .ai_maxdata = 0xffff,
424 .ai_fifo_depth = 512,
425 .alwaysdither = 1,
426 .gainlkup = ai_gain_4,
427 .ai_speed = 5000,
428 .caldac = { ad8804_debug },
429 },
430 [BOARD_PCI6035E] = {
431 .name = "pci-6035e",
432 .n_adchan = 16,
433 .ai_maxdata = 0xffff,
434 .ai_fifo_depth = 512,
435 .alwaysdither = 1,
436 .gainlkup = ai_gain_4,
437 .ai_speed = 5000,
438 .n_aochan = 2,
439 .ao_maxdata = 0x0fff,
440 .ao_range_table = &range_bipolar10,
441 .ao_speed = 100000,
442 .caldac = { ad8804_debug },
443 },
444 [BOARD_PCI6052E] = {
445 .name = "pci-6052e",
446 .n_adchan = 16,
447 .ai_maxdata = 0xffff,
448 .ai_fifo_depth = 512,
449 .alwaysdither = 1,
450 .gainlkup = ai_gain_16,
451 .ai_speed = 3000,
452 .n_aochan = 2,
453 .ao_maxdata = 0xffff,
454 .ao_fifo_depth = 2048,
455 .ao_range_table = &range_ni_E_ao_ext,
456 .ao_speed = 3000,
457 /* manual is wrong */
458 .caldac = { ad8804_debug, ad8804_debug, ad8522 },
459 },
460 [BOARD_PCI6110] = {
461 .name = "pci-6110",
462 .n_adchan = 4,
463 .ai_maxdata = 0x0fff,
464 .ai_fifo_depth = 8192,
465 .alwaysdither = 0,
466 .gainlkup = ai_gain_611x,
467 .ai_speed = 200,
468 .n_aochan = 2,
469 .ao_maxdata = 0xffff,
470 .reg_type = ni_reg_611x,
471 .ao_range_table = &range_bipolar10,
472 .ao_fifo_depth = 2048,
473 .ao_speed = 250,
474 .caldac = { ad8804, ad8804 },
475 },
476 [BOARD_PCI6111] = {
477 .name = "pci-6111",
478 .n_adchan = 2,
479 .ai_maxdata = 0x0fff,
480 .ai_fifo_depth = 8192,
481 .gainlkup = ai_gain_611x,
482 .ai_speed = 200,
483 .n_aochan = 2,
484 .ao_maxdata = 0xffff,
485 .reg_type = ni_reg_611x,
486 .ao_range_table = &range_bipolar10,
487 .ao_fifo_depth = 2048,
488 .ao_speed = 250,
489 .caldac = { ad8804, ad8804 },
490 },
491 #if 0
492 /* The 6115 boards probably need their own driver */
493 [BOARD_PCI6115] = { /* .device_id = 0x2ed0, */
494 .name = "pci-6115",
495 .n_adchan = 4,
496 .ai_maxdata = 0x0fff,
497 .ai_fifo_depth = 8192,
498 .gainlkup = ai_gain_611x,
499 .ai_speed = 100,
500 .n_aochan = 2,
501 .ao_maxdata = 0xffff,
502 .ao_671x = 1,
503 .ao_fifo_depth = 2048,
504 .ao_speed = 250,
505 .reg_611x = 1,
506 /* XXX */
507 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
508 },
509 #endif
510 #if 0
511 [BOARD_PXI6115] = { /* .device_id = ????, */
512 .name = "pxi-6115",
513 .n_adchan = 4,
514 .ai_maxdata = 0x0fff,
515 .ai_fifo_depth = 8192,
516 .gainlkup = ai_gain_611x,
517 .ai_speed = 100,
518 .n_aochan = 2,
519 .ao_maxdata = 0xffff,
520 .ao_671x = 1,
521 .ao_fifo_depth = 2048,
522 .ao_speed = 250,
523 .reg_611x = 1,
524 /* XXX */
525 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
526 },
527 #endif
528 [BOARD_PCI6711] = {
529 .name = "pci-6711",
530 .n_aochan = 4,
531 .ao_maxdata = 0x0fff,
532 /* data sheet says 8192, but fifo really holds 16384 samples */
533 .ao_fifo_depth = 16384,
534 .ao_range_table = &range_bipolar10,
535 .ao_speed = 1000,
536 .reg_type = ni_reg_6711,
537 .caldac = { ad8804_debug },
538 },
539 [BOARD_PXI6711] = {
540 .name = "pxi-6711",
541 .n_aochan = 4,
542 .ao_maxdata = 0x0fff,
543 .ao_fifo_depth = 16384,
544 .ao_range_table = &range_bipolar10,
545 .ao_speed = 1000,
546 .reg_type = ni_reg_6711,
547 .caldac = { ad8804_debug },
548 },
549 [BOARD_PCI6713] = {
550 .name = "pci-6713",
551 .n_aochan = 8,
552 .ao_maxdata = 0x0fff,
553 .ao_fifo_depth = 16384,
554 .ao_range_table = &range_bipolar10,
555 .ao_speed = 1000,
556 .reg_type = ni_reg_6713,
557 .caldac = { ad8804_debug, ad8804_debug },
558 },
559 [BOARD_PXI6713] = {
560 .name = "pxi-6713",
561 .n_aochan = 8,
562 .ao_maxdata = 0x0fff,
563 .ao_fifo_depth = 16384,
564 .ao_range_table = &range_bipolar10,
565 .ao_speed = 1000,
566 .reg_type = ni_reg_6713,
567 .caldac = { ad8804_debug, ad8804_debug },
568 },
569 [BOARD_PCI6731] = {
570 .name = "pci-6731",
571 .n_aochan = 4,
572 .ao_maxdata = 0xffff,
573 .ao_fifo_depth = 8192,
574 .ao_range_table = &range_bipolar10,
575 .ao_speed = 1000,
576 .reg_type = ni_reg_6711,
577 .caldac = { ad8804_debug },
578 },
579 #if 0
580 [BOARD_PXI6731] = { /* .device_id = ????, */
581 .name = "pxi-6731",
582 .n_aochan = 4,
583 .ao_maxdata = 0xffff,
584 .ao_fifo_depth = 8192,
585 .ao_range_table = &range_bipolar10,
586 .reg_type = ni_reg_6711,
587 .caldac = { ad8804_debug },
588 },
589 #endif
590 [BOARD_PCI6733] = {
591 .name = "pci-6733",
592 .n_aochan = 8,
593 .ao_maxdata = 0xffff,
594 .ao_fifo_depth = 16384,
595 .ao_range_table = &range_bipolar10,
596 .ao_speed = 1000,
597 .reg_type = ni_reg_6713,
598 .caldac = { ad8804_debug, ad8804_debug },
599 },
600 [BOARD_PXI6733] = {
601 .name = "pxi-6733",
602 .n_aochan = 8,
603 .ao_maxdata = 0xffff,
604 .ao_fifo_depth = 16384,
605 .ao_range_table = &range_bipolar10,
606 .ao_speed = 1000,
607 .reg_type = ni_reg_6713,
608 .caldac = { ad8804_debug, ad8804_debug },
609 },
610 [BOARD_PXI6071E] = {
611 .name = "pxi-6071e",
612 .n_adchan = 64,
613 .ai_maxdata = 0x0fff,
614 .ai_fifo_depth = 512,
615 .alwaysdither = 1,
616 .gainlkup = ai_gain_16,
617 .ai_speed = 800,
618 .n_aochan = 2,
619 .ao_maxdata = 0x0fff,
620 .ao_fifo_depth = 2048,
621 .ao_range_table = &range_ni_E_ao_ext,
622 .ao_speed = 1000,
623 .caldac = { ad8804_debug },
624 },
625 [BOARD_PXI6070E] = {
626 .name = "pxi-6070e",
627 .n_adchan = 16,
628 .ai_maxdata = 0x0fff,
629 .ai_fifo_depth = 512,
630 .alwaysdither = 1,
631 .gainlkup = ai_gain_16,
632 .ai_speed = 800,
633 .n_aochan = 2,
634 .ao_maxdata = 0x0fff,
635 .ao_fifo_depth = 2048,
636 .ao_range_table = &range_ni_E_ao_ext,
637 .ao_speed = 1000,
638 .caldac = { ad8804_debug },
639 },
640 [BOARD_PXI6052E] = {
641 .name = "pxi-6052e",
642 .n_adchan = 16,
643 .ai_maxdata = 0xffff,
644 .ai_fifo_depth = 512,
645 .alwaysdither = 1,
646 .gainlkup = ai_gain_16,
647 .ai_speed = 3000,
648 .n_aochan = 2,
649 .ao_maxdata = 0xffff,
650 .ao_fifo_depth = 2048,
651 .ao_range_table = &range_ni_E_ao_ext,
652 .ao_speed = 3000,
653 .caldac = { mb88341, mb88341, ad8522 },
654 },
655 [BOARD_PXI6031E] = {
656 .name = "pxi-6031e",
657 .n_adchan = 64,
658 .ai_maxdata = 0xffff,
659 .ai_fifo_depth = 512,
660 .alwaysdither = 1,
661 .gainlkup = ai_gain_14,
662 .ai_speed = 10000,
663 .n_aochan = 2,
664 .ao_maxdata = 0xffff,
665 .ao_fifo_depth = 2048,
666 .ao_range_table = &range_ni_E_ao_ext,
667 .ao_speed = 10000,
668 .caldac = { dac8800, dac8043, ad8522 },
669 },
670 [BOARD_PCI6036E] = {
671 .name = "pci-6036e",
672 .n_adchan = 16,
673 .ai_maxdata = 0xffff,
674 .ai_fifo_depth = 512,
675 .alwaysdither = 1,
676 .gainlkup = ai_gain_4,
677 .ai_speed = 5000,
678 .n_aochan = 2,
679 .ao_maxdata = 0xffff,
680 .ao_range_table = &range_bipolar10,
681 .ao_speed = 100000,
682 .caldac = { ad8804_debug },
683 },
684 [BOARD_PCI6220] = {
685 .name = "pci-6220",
686 .n_adchan = 16,
687 .ai_maxdata = 0xffff,
688 .ai_fifo_depth = 512, /* FIXME: guess */
689 .gainlkup = ai_gain_622x,
690 .ai_speed = 4000,
691 .reg_type = ni_reg_622x,
692 .caldac = { caldac_none },
693 },
694 [BOARD_PXI6220] = {
695 .name = "pxi-6220",
696 .n_adchan = 16,
697 .ai_maxdata = 0xffff,
698 .ai_fifo_depth = 512, /* FIXME: guess */
699 .gainlkup = ai_gain_622x,
700 .ai_speed = 4000,
701 .reg_type = ni_reg_622x,
702 .caldac = { caldac_none },
703 .dio_speed = 1000,
704 },
705 [BOARD_PCI6221] = {
706 .name = "pci-6221",
707 .n_adchan = 16,
708 .ai_maxdata = 0xffff,
709 .ai_fifo_depth = 4095,
710 .gainlkup = ai_gain_622x,
711 .ai_speed = 4000,
712 .n_aochan = 2,
713 .ao_maxdata = 0xffff,
714 .ao_fifo_depth = 8191,
715 .ao_range_table = &range_bipolar10,
716 .reg_type = ni_reg_622x,
717 .ao_speed = 1200,
718 .caldac = { caldac_none },
719 .dio_speed = 1000,
720 },
721 [BOARD_PCI6221_37PIN] = {
722 .name = "pci-6221_37pin",
723 .n_adchan = 16,
724 .ai_maxdata = 0xffff,
725 .ai_fifo_depth = 4095,
726 .gainlkup = ai_gain_622x,
727 .ai_speed = 4000,
728 .n_aochan = 2,
729 .ao_maxdata = 0xffff,
730 .ao_fifo_depth = 8191,
731 .ao_range_table = &range_bipolar10,
732 .reg_type = ni_reg_622x,
733 .ao_speed = 1200,
734 .caldac = { caldac_none },
735 },
736 [BOARD_PXI6221] = {
737 .name = "pxi-6221",
738 .n_adchan = 16,
739 .ai_maxdata = 0xffff,
740 .ai_fifo_depth = 4095,
741 .gainlkup = ai_gain_622x,
742 .ai_speed = 4000,
743 .n_aochan = 2,
744 .ao_maxdata = 0xffff,
745 .ao_fifo_depth = 8191,
746 .ao_range_table = &range_bipolar10,
747 .reg_type = ni_reg_622x,
748 .ao_speed = 1200,
749 .caldac = { caldac_none },
750 .dio_speed = 1000,
751 },
752 [BOARD_PCI6224] = {
753 .name = "pci-6224",
754 .n_adchan = 32,
755 .ai_maxdata = 0xffff,
756 .ai_fifo_depth = 4095,
757 .gainlkup = ai_gain_622x,
758 .ai_speed = 4000,
759 .reg_type = ni_reg_622x,
760 .has_32dio_chan = 1,
761 .caldac = { caldac_none },
762 .dio_speed = 1000,
763 },
764 [BOARD_PXI6224] = {
765 .name = "pxi-6224",
766 .n_adchan = 32,
767 .ai_maxdata = 0xffff,
768 .ai_fifo_depth = 4095,
769 .gainlkup = ai_gain_622x,
770 .ai_speed = 4000,
771 .reg_type = ni_reg_622x,
772 .has_32dio_chan = 1,
773 .caldac = { caldac_none },
774 .dio_speed = 1000,
775 },
776 [BOARD_PCI6225] = {
777 .name = "pci-6225",
778 .n_adchan = 80,
779 .ai_maxdata = 0xffff,
780 .ai_fifo_depth = 4095,
781 .gainlkup = ai_gain_622x,
782 .ai_speed = 4000,
783 .n_aochan = 2,
784 .ao_maxdata = 0xffff,
785 .ao_fifo_depth = 8191,
786 .ao_range_table = &range_bipolar10,
787 .reg_type = ni_reg_622x,
788 .ao_speed = 1200,
789 .has_32dio_chan = 1,
790 .caldac = { caldac_none },
791 .dio_speed = 1000,
792 },
793 [BOARD_PXI6225] = {
794 .name = "pxi-6225",
795 .n_adchan = 80,
796 .ai_maxdata = 0xffff,
797 .ai_fifo_depth = 4095,
798 .gainlkup = ai_gain_622x,
799 .ai_speed = 4000,
800 .n_aochan = 2,
801 .ao_maxdata = 0xffff,
802 .ao_fifo_depth = 8191,
803 .ao_range_table = &range_bipolar10,
804 .reg_type = ni_reg_622x,
805 .ao_speed = 1200,
806 .has_32dio_chan = 1,
807 .caldac = { caldac_none },
808 .dio_speed = 1000,
809 },
810 [BOARD_PCI6229] = {
811 .name = "pci-6229",
812 .n_adchan = 32,
813 .ai_maxdata = 0xffff,
814 .ai_fifo_depth = 4095,
815 .gainlkup = ai_gain_622x,
816 .ai_speed = 4000,
817 .n_aochan = 4,
818 .ao_maxdata = 0xffff,
819 .ao_fifo_depth = 8191,
820 .ao_range_table = &range_bipolar10,
821 .reg_type = ni_reg_622x,
822 .ao_speed = 1200,
823 .has_32dio_chan = 1,
824 .caldac = { caldac_none },
825 },
826 [BOARD_PXI6229] = {
827 .name = "pxi-6229",
828 .n_adchan = 32,
829 .ai_maxdata = 0xffff,
830 .ai_fifo_depth = 4095,
831 .gainlkup = ai_gain_622x,
832 .ai_speed = 4000,
833 .n_aochan = 4,
834 .ao_maxdata = 0xffff,
835 .ao_fifo_depth = 8191,
836 .ao_range_table = &range_bipolar10,
837 .reg_type = ni_reg_622x,
838 .ao_speed = 1200,
839 .has_32dio_chan = 1,
840 .caldac = { caldac_none },
841 .dio_speed = 1000,
842 },
843 [BOARD_PCI6250] = {
844 .name = "pci-6250",
845 .n_adchan = 16,
846 .ai_maxdata = 0xffff,
847 .ai_fifo_depth = 4095,
848 .gainlkup = ai_gain_628x,
849 .ai_speed = 800,
850 .reg_type = ni_reg_625x,
851 .caldac = { caldac_none },
852 },
853 [BOARD_PXI6250] = {
854 .name = "pxi-6250",
855 .n_adchan = 16,
856 .ai_maxdata = 0xffff,
857 .ai_fifo_depth = 4095,
858 .gainlkup = ai_gain_628x,
859 .ai_speed = 800,
860 .reg_type = ni_reg_625x,
861 .caldac = { caldac_none },
862 .dio_speed = 100,
863 },
864 [BOARD_PCI6251] = {
865 .name = "pci-6251",
866 .n_adchan = 16,
867 .ai_maxdata = 0xffff,
868 .ai_fifo_depth = 4095,
869 .gainlkup = ai_gain_628x,
870 .ai_speed = 800,
871 .n_aochan = 2,
872 .ao_maxdata = 0xffff,
873 .ao_fifo_depth = 8191,
874 .ao_range_table = &range_ni_M_625x_ao,
875 .reg_type = ni_reg_625x,
876 .ao_speed = 350,
877 .caldac = { caldac_none },
878 .dio_speed = 100,
879 },
880 [BOARD_PXI6251] = {
881 .name = "pxi-6251",
882 .n_adchan = 16,
883 .ai_maxdata = 0xffff,
884 .ai_fifo_depth = 4095,
885 .gainlkup = ai_gain_628x,
886 .ai_speed = 800,
887 .n_aochan = 2,
888 .ao_maxdata = 0xffff,
889 .ao_fifo_depth = 8191,
890 .ao_range_table = &range_ni_M_625x_ao,
891 .reg_type = ni_reg_625x,
892 .ao_speed = 350,
893 .caldac = { caldac_none },
894 .dio_speed = 100,
895 },
896 [BOARD_PCIE6251] = {
897 .name = "pcie-6251",
898 .alt_route_name = "pci-6251",
899 .n_adchan = 16,
900 .ai_maxdata = 0xffff,
901 .ai_fifo_depth = 4095,
902 .gainlkup = ai_gain_628x,
903 .ai_speed = 800,
904 .n_aochan = 2,
905 .ao_maxdata = 0xffff,
906 .ao_fifo_depth = 8191,
907 .ao_range_table = &range_ni_M_625x_ao,
908 .reg_type = ni_reg_625x,
909 .ao_speed = 350,
910 .caldac = { caldac_none },
911 .dio_speed = 100,
912 },
913 [BOARD_PXIE6251] = {
914 .name = "pxie-6251",
915 .n_adchan = 16,
916 .ai_maxdata = 0xffff,
917 .ai_fifo_depth = 4095,
918 .gainlkup = ai_gain_628x,
919 .ai_speed = 800,
920 .n_aochan = 2,
921 .ao_maxdata = 0xffff,
922 .ao_fifo_depth = 8191,
923 .ao_range_table = &range_ni_M_625x_ao,
924 .reg_type = ni_reg_625x,
925 .ao_speed = 350,
926 .caldac = { caldac_none },
927 .dio_speed = 100,
928 },
929 [BOARD_PCI6254] = {
930 .name = "pci-6254",
931 .n_adchan = 32,
932 .ai_maxdata = 0xffff,
933 .ai_fifo_depth = 4095,
934 .gainlkup = ai_gain_628x,
935 .ai_speed = 800,
936 .reg_type = ni_reg_625x,
937 .has_32dio_chan = 1,
938 .caldac = { caldac_none },
939 },
940 [BOARD_PXI6254] = {
941 .name = "pxi-6254",
942 .n_adchan = 32,
943 .ai_maxdata = 0xffff,
944 .ai_fifo_depth = 4095,
945 .gainlkup = ai_gain_628x,
946 .ai_speed = 800,
947 .reg_type = ni_reg_625x,
948 .has_32dio_chan = 1,
949 .caldac = { caldac_none },
950 .dio_speed = 100,
951 },
952 [BOARD_PCI6259] = {
953 .name = "pci-6259",
954 .n_adchan = 32,
955 .ai_maxdata = 0xffff,
956 .ai_fifo_depth = 4095,
957 .gainlkup = ai_gain_628x,
958 .ai_speed = 800,
959 .n_aochan = 4,
960 .ao_maxdata = 0xffff,
961 .ao_fifo_depth = 8191,
962 .ao_range_table = &range_ni_M_625x_ao,
963 .reg_type = ni_reg_625x,
964 .ao_speed = 350,
965 .has_32dio_chan = 1,
966 .caldac = { caldac_none },
967 },
968 [BOARD_PXI6259] = {
969 .name = "pxi-6259",
970 .n_adchan = 32,
971 .ai_maxdata = 0xffff,
972 .ai_fifo_depth = 4095,
973 .gainlkup = ai_gain_628x,
974 .ai_speed = 800,
975 .n_aochan = 4,
976 .ao_maxdata = 0xffff,
977 .ao_fifo_depth = 8191,
978 .ao_range_table = &range_ni_M_625x_ao,
979 .reg_type = ni_reg_625x,
980 .ao_speed = 350,
981 .has_32dio_chan = 1,
982 .caldac = { caldac_none },
983 .dio_speed = 100,
984 },
985 [BOARD_PCIE6259] = {
986 .name = "pcie-6259",
987 .alt_route_name = "pci-6259",
988 .n_adchan = 32,
989 .ai_maxdata = 0xffff,
990 .ai_fifo_depth = 4095,
991 .gainlkup = ai_gain_628x,
992 .ai_speed = 800,
993 .n_aochan = 4,
994 .ao_maxdata = 0xffff,
995 .ao_fifo_depth = 8191,
996 .ao_range_table = &range_ni_M_625x_ao,
997 .reg_type = ni_reg_625x,
998 .ao_speed = 350,
999 .has_32dio_chan = 1,
1000 .caldac = { caldac_none },
1001 },
1002 [BOARD_PXIE6259] = {
1003 .name = "pxie-6259",
1004 .n_adchan = 32,
1005 .ai_maxdata = 0xffff,
1006 .ai_fifo_depth = 4095,
1007 .gainlkup = ai_gain_628x,
1008 .ai_speed = 800,
1009 .n_aochan = 4,
1010 .ao_maxdata = 0xffff,
1011 .ao_fifo_depth = 8191,
1012 .ao_range_table = &range_ni_M_625x_ao,
1013 .reg_type = ni_reg_625x,
1014 .ao_speed = 350,
1015 .has_32dio_chan = 1,
1016 .caldac = { caldac_none },
1017 .dio_speed = 100,
1018 },
1019 [BOARD_PCI6280] = {
1020 .name = "pci-6280",
1021 .n_adchan = 16,
1022 .ai_maxdata = 0x3ffff,
1023 .ai_fifo_depth = 2047,
1024 .gainlkup = ai_gain_628x,
1025 .ai_speed = 1600,
1026 .ao_fifo_depth = 8191,
1027 .reg_type = ni_reg_628x,
1028 .caldac = { caldac_none },
1029 },
1030 [BOARD_PXI6280] = {
1031 .name = "pxi-6280",
1032 .n_adchan = 16,
1033 .ai_maxdata = 0x3ffff,
1034 .ai_fifo_depth = 2047,
1035 .gainlkup = ai_gain_628x,
1036 .ai_speed = 1600,
1037 .ao_fifo_depth = 8191,
1038 .reg_type = ni_reg_628x,
1039 .caldac = { caldac_none },
1040 .dio_speed = 100,
1041 },
1042 [BOARD_PCI6281] = {
1043 .name = "pci-6281",
1044 .n_adchan = 16,
1045 .ai_maxdata = 0x3ffff,
1046 .ai_fifo_depth = 2047,
1047 .gainlkup = ai_gain_628x,
1048 .ai_speed = 1600,
1049 .n_aochan = 2,
1050 .ao_maxdata = 0xffff,
1051 .ao_fifo_depth = 8191,
1052 .ao_range_table = &range_ni_M_628x_ao,
1053 .reg_type = ni_reg_628x,
1054 .ao_speed = 350,
1055 .caldac = { caldac_none },
1056 .dio_speed = 100,
1057 },
1058 [BOARD_PXI6281] = {
1059 .name = "pxi-6281",
1060 .n_adchan = 16,
1061 .ai_maxdata = 0x3ffff,
1062 .ai_fifo_depth = 2047,
1063 .gainlkup = ai_gain_628x,
1064 .ai_speed = 1600,
1065 .n_aochan = 2,
1066 .ao_maxdata = 0xffff,
1067 .ao_fifo_depth = 8191,
1068 .ao_range_table = &range_ni_M_628x_ao,
1069 .reg_type = ni_reg_628x,
1070 .ao_speed = 350,
1071 .caldac = { caldac_none },
1072 .dio_speed = 100,
1073 },
1074 [BOARD_PCI6284] = {
1075 .name = "pci-6284",
1076 .n_adchan = 32,
1077 .ai_maxdata = 0x3ffff,
1078 .ai_fifo_depth = 2047,
1079 .gainlkup = ai_gain_628x,
1080 .ai_speed = 1600,
1081 .reg_type = ni_reg_628x,
1082 .has_32dio_chan = 1,
1083 .caldac = { caldac_none },
1084 },
1085 [BOARD_PXI6284] = {
1086 .name = "pxi-6284",
1087 .n_adchan = 32,
1088 .ai_maxdata = 0x3ffff,
1089 .ai_fifo_depth = 2047,
1090 .gainlkup = ai_gain_628x,
1091 .ai_speed = 1600,
1092 .reg_type = ni_reg_628x,
1093 .has_32dio_chan = 1,
1094 .caldac = { caldac_none },
1095 .dio_speed = 100,
1096 },
1097 [BOARD_PCI6289] = {
1098 .name = "pci-6289",
1099 .n_adchan = 32,
1100 .ai_maxdata = 0x3ffff,
1101 .ai_fifo_depth = 2047,
1102 .gainlkup = ai_gain_628x,
1103 .ai_speed = 1600,
1104 .n_aochan = 4,
1105 .ao_maxdata = 0xffff,
1106 .ao_fifo_depth = 8191,
1107 .ao_range_table = &range_ni_M_628x_ao,
1108 .reg_type = ni_reg_628x,
1109 .ao_speed = 350,
1110 .has_32dio_chan = 1,
1111 .caldac = { caldac_none },
1112 },
1113 [BOARD_PXI6289] = {
1114 .name = "pxi-6289",
1115 .n_adchan = 32,
1116 .ai_maxdata = 0x3ffff,
1117 .ai_fifo_depth = 2047,
1118 .gainlkup = ai_gain_628x,
1119 .ai_speed = 1600,
1120 .n_aochan = 4,
1121 .ao_maxdata = 0xffff,
1122 .ao_fifo_depth = 8191,
1123 .ao_range_table = &range_ni_M_628x_ao,
1124 .reg_type = ni_reg_628x,
1125 .ao_speed = 350,
1126 .has_32dio_chan = 1,
1127 .caldac = { caldac_none },
1128 .dio_speed = 100,
1129 },
1130 [BOARD_PCI6143] = {
1131 .name = "pci-6143",
1132 .n_adchan = 8,
1133 .ai_maxdata = 0xffff,
1134 .ai_fifo_depth = 1024,
1135 .gainlkup = ai_gain_6143,
1136 .ai_speed = 4000,
1137 .reg_type = ni_reg_6143,
1138 .caldac = { ad8804_debug, ad8804_debug },
1139 },
1140 [BOARD_PXI6143] = {
1141 .name = "pxi-6143",
1142 .n_adchan = 8,
1143 .ai_maxdata = 0xffff,
1144 .ai_fifo_depth = 1024,
1145 .gainlkup = ai_gain_6143,
1146 .ai_speed = 4000,
1147 .reg_type = ni_reg_6143,
1148 .caldac = { ad8804_debug, ad8804_debug },
1149 },
1150 };
1151
1152 #include "ni_mio_common.c"
1153
pcimio_ai_change(struct comedi_device * dev,struct comedi_subdevice * s)1154 static int pcimio_ai_change(struct comedi_device *dev,
1155 struct comedi_subdevice *s)
1156 {
1157 struct ni_private *devpriv = dev->private;
1158 int ret;
1159
1160 ret = mite_buf_change(devpriv->ai_mite_ring, s);
1161 if (ret < 0)
1162 return ret;
1163
1164 return 0;
1165 }
1166
pcimio_ao_change(struct comedi_device * dev,struct comedi_subdevice * s)1167 static int pcimio_ao_change(struct comedi_device *dev,
1168 struct comedi_subdevice *s)
1169 {
1170 struct ni_private *devpriv = dev->private;
1171 int ret;
1172
1173 ret = mite_buf_change(devpriv->ao_mite_ring, s);
1174 if (ret < 0)
1175 return ret;
1176
1177 return 0;
1178 }
1179
pcimio_gpct0_change(struct comedi_device * dev,struct comedi_subdevice * s)1180 static int pcimio_gpct0_change(struct comedi_device *dev,
1181 struct comedi_subdevice *s)
1182 {
1183 struct ni_private *devpriv = dev->private;
1184 int ret;
1185
1186 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s);
1187 if (ret < 0)
1188 return ret;
1189
1190 return 0;
1191 }
1192
pcimio_gpct1_change(struct comedi_device * dev,struct comedi_subdevice * s)1193 static int pcimio_gpct1_change(struct comedi_device *dev,
1194 struct comedi_subdevice *s)
1195 {
1196 struct ni_private *devpriv = dev->private;
1197 int ret;
1198
1199 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s);
1200 if (ret < 0)
1201 return ret;
1202
1203 return 0;
1204 }
1205
pcimio_dio_change(struct comedi_device * dev,struct comedi_subdevice * s)1206 static int pcimio_dio_change(struct comedi_device *dev,
1207 struct comedi_subdevice *s)
1208 {
1209 struct ni_private *devpriv = dev->private;
1210 int ret;
1211
1212 ret = mite_buf_change(devpriv->cdo_mite_ring, s);
1213 if (ret < 0)
1214 return ret;
1215
1216 return 0;
1217 }
1218
m_series_init_eeprom_buffer(struct comedi_device * dev)1219 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1220 {
1221 struct ni_private *devpriv = dev->private;
1222 struct mite *mite = devpriv->mite;
1223 resource_size_t daq_phys_addr;
1224 static const int start_cal_eeprom = 0x400;
1225 static const unsigned int window_size = 10;
1226 unsigned int old_iodwbsr_bits;
1227 unsigned int old_iodwbsr1_bits;
1228 unsigned int old_iodwcr1_bits;
1229 int i;
1230
1231 /* IO Window 1 needs to be temporarily mapped to read the eeprom */
1232 daq_phys_addr = pci_resource_start(mite->pcidev, 1);
1233
1234 old_iodwbsr_bits = readl(mite->mmio + MITE_IODWBSR);
1235 old_iodwbsr1_bits = readl(mite->mmio + MITE_IODWBSR_1);
1236 old_iodwcr1_bits = readl(mite->mmio + MITE_IODWCR_1);
1237 writel(0x0, mite->mmio + MITE_IODWBSR);
1238 writel(((0x80 | window_size) | daq_phys_addr),
1239 mite->mmio + MITE_IODWBSR_1);
1240 writel(0x1 | old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1241 writel(0xf, mite->mmio + 0x30);
1242
1243 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1244 devpriv->eeprom_buffer[i] = ni_readb(dev, start_cal_eeprom + i);
1245
1246 writel(old_iodwbsr1_bits, mite->mmio + MITE_IODWBSR_1);
1247 writel(old_iodwbsr_bits, mite->mmio + MITE_IODWBSR);
1248 writel(old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1249 writel(0x0, mite->mmio + 0x30);
1250 }
1251
init_6143(struct comedi_device * dev)1252 static void init_6143(struct comedi_device *dev)
1253 {
1254 const struct ni_board_struct *board = dev->board_ptr;
1255 struct ni_private *devpriv = dev->private;
1256
1257 /* Disable interrupts */
1258 ni_stc_writew(dev, 0, NISTC_INT_CTRL_REG);
1259
1260 /* Initialise 6143 AI specific bits */
1261
1262 /* Set G0,G1 DMA mode to E series version */
1263 ni_writeb(dev, 0x00, NI6143_MAGIC_REG);
1264 /* Set EOCMode, ADCMode and pipelinedelay */
1265 ni_writeb(dev, 0x80, NI6143_PIPELINE_DELAY_REG);
1266 /* Set EOC Delay */
1267 ni_writeb(dev, 0x00, NI6143_EOC_SET_REG);
1268
1269 /* Set the FIFO half full level */
1270 ni_writel(dev, board->ai_fifo_depth / 2, NI6143_AI_FIFO_FLAG_REG);
1271
1272 /* Strobe Relay disable bit */
1273 devpriv->ai_calib_source_enabled = 0;
1274 ni_writew(dev, devpriv->ai_calib_source | NI6143_CALIB_CHAN_RELAY_OFF,
1275 NI6143_CALIB_CHAN_REG);
1276 ni_writew(dev, devpriv->ai_calib_source, NI6143_CALIB_CHAN_REG);
1277 }
1278
pcimio_detach(struct comedi_device * dev)1279 static void pcimio_detach(struct comedi_device *dev)
1280 {
1281 struct ni_private *devpriv = dev->private;
1282
1283 mio_common_detach(dev);
1284 if (dev->irq)
1285 free_irq(dev->irq, dev);
1286 if (devpriv) {
1287 mite_free_ring(devpriv->ai_mite_ring);
1288 mite_free_ring(devpriv->ao_mite_ring);
1289 mite_free_ring(devpriv->cdo_mite_ring);
1290 mite_free_ring(devpriv->gpct_mite_ring[0]);
1291 mite_free_ring(devpriv->gpct_mite_ring[1]);
1292 mite_detach(devpriv->mite);
1293 }
1294 if (dev->mmio)
1295 iounmap(dev->mmio);
1296 comedi_pci_disable(dev);
1297 }
1298
pcimio_auto_attach(struct comedi_device * dev,unsigned long context)1299 static int pcimio_auto_attach(struct comedi_device *dev,
1300 unsigned long context)
1301 {
1302 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1303 const struct ni_board_struct *board = NULL;
1304 struct ni_private *devpriv;
1305 unsigned int irq;
1306 int ret;
1307
1308 if (context < ARRAY_SIZE(ni_boards))
1309 board = &ni_boards[context];
1310 if (!board)
1311 return -ENODEV;
1312 dev->board_ptr = board;
1313 dev->board_name = board->name;
1314
1315 ret = comedi_pci_enable(dev);
1316 if (ret)
1317 return ret;
1318
1319 ret = ni_alloc_private(dev);
1320 if (ret)
1321 return ret;
1322 devpriv = dev->private;
1323
1324 devpriv->mite = mite_attach(dev, false); /* use win0 */
1325 if (!devpriv->mite)
1326 return -ENOMEM;
1327
1328 if (board->reg_type & ni_reg_m_series_mask)
1329 devpriv->is_m_series = 1;
1330 if (board->reg_type & ni_reg_6xxx_mask)
1331 devpriv->is_6xxx = 1;
1332 if (board->reg_type == ni_reg_611x)
1333 devpriv->is_611x = 1;
1334 if (board->reg_type == ni_reg_6143)
1335 devpriv->is_6143 = 1;
1336 if (board->reg_type == ni_reg_622x)
1337 devpriv->is_622x = 1;
1338 if (board->reg_type == ni_reg_625x)
1339 devpriv->is_625x = 1;
1340 if (board->reg_type == ni_reg_628x)
1341 devpriv->is_628x = 1;
1342 if (board->reg_type & ni_reg_67xx_mask)
1343 devpriv->is_67xx = 1;
1344 if (board->reg_type == ni_reg_6711)
1345 devpriv->is_6711 = 1;
1346 if (board->reg_type == ni_reg_6713)
1347 devpriv->is_6713 = 1;
1348
1349 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1350 if (!devpriv->ai_mite_ring)
1351 return -ENOMEM;
1352 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1353 if (!devpriv->ao_mite_ring)
1354 return -ENOMEM;
1355 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1356 if (!devpriv->cdo_mite_ring)
1357 return -ENOMEM;
1358 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1359 if (!devpriv->gpct_mite_ring[0])
1360 return -ENOMEM;
1361 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1362 if (!devpriv->gpct_mite_ring[1])
1363 return -ENOMEM;
1364
1365 if (devpriv->is_m_series)
1366 m_series_init_eeprom_buffer(dev);
1367 if (devpriv->is_6143)
1368 init_6143(dev);
1369
1370 irq = pcidev->irq;
1371 if (irq) {
1372 ret = request_irq(irq, ni_E_interrupt, IRQF_SHARED,
1373 dev->board_name, dev);
1374 if (ret == 0)
1375 dev->irq = irq;
1376 }
1377
1378 ret = ni_E_init(dev, 0, 1);
1379 if (ret < 0)
1380 return ret;
1381
1382 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1383 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1384 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1385 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1386 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1387
1388 return 0;
1389 }
1390
1391 static struct comedi_driver ni_pcimio_driver = {
1392 .driver_name = "ni_pcimio",
1393 .module = THIS_MODULE,
1394 .auto_attach = pcimio_auto_attach,
1395 .detach = pcimio_detach,
1396 };
1397
ni_pcimio_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)1398 static int ni_pcimio_pci_probe(struct pci_dev *dev,
1399 const struct pci_device_id *id)
1400 {
1401 return comedi_pci_auto_config(dev, &ni_pcimio_driver, id->driver_data);
1402 }
1403
1404 static const struct pci_device_id ni_pcimio_pci_table[] = {
1405 { PCI_VDEVICE(NI, 0x0162), BOARD_PCIMIO_16XE_50 }, /* 0x1620? */
1406 { PCI_VDEVICE(NI, 0x1170), BOARD_PCIMIO_16XE_10 },
1407 { PCI_VDEVICE(NI, 0x1180), BOARD_PCIMIO_16E_1 },
1408 { PCI_VDEVICE(NI, 0x1190), BOARD_PCIMIO_16E_4 },
1409 { PCI_VDEVICE(NI, 0x11b0), BOARD_PXI6070E },
1410 { PCI_VDEVICE(NI, 0x11c0), BOARD_PXI6040E },
1411 { PCI_VDEVICE(NI, 0x11d0), BOARD_PXI6030E },
1412 { PCI_VDEVICE(NI, 0x1270), BOARD_PCI6032E },
1413 { PCI_VDEVICE(NI, 0x1330), BOARD_PCI6031E },
1414 { PCI_VDEVICE(NI, 0x1340), BOARD_PCI6033E },
1415 { PCI_VDEVICE(NI, 0x1350), BOARD_PCI6071E },
1416 { PCI_VDEVICE(NI, 0x14e0), BOARD_PCI6110 },
1417 { PCI_VDEVICE(NI, 0x14f0), BOARD_PCI6111 },
1418 { PCI_VDEVICE(NI, 0x1580), BOARD_PXI6031E },
1419 { PCI_VDEVICE(NI, 0x15b0), BOARD_PXI6071E },
1420 { PCI_VDEVICE(NI, 0x1880), BOARD_PCI6711 },
1421 { PCI_VDEVICE(NI, 0x1870), BOARD_PCI6713 },
1422 { PCI_VDEVICE(NI, 0x18b0), BOARD_PCI6052E },
1423 { PCI_VDEVICE(NI, 0x18c0), BOARD_PXI6052E },
1424 { PCI_VDEVICE(NI, 0x2410), BOARD_PCI6733 },
1425 { PCI_VDEVICE(NI, 0x2420), BOARD_PXI6733 },
1426 { PCI_VDEVICE(NI, 0x2430), BOARD_PCI6731 },
1427 { PCI_VDEVICE(NI, 0x2890), BOARD_PCI6036E },
1428 { PCI_VDEVICE(NI, 0x28c0), BOARD_PCI6014 },
1429 { PCI_VDEVICE(NI, 0x2a60), BOARD_PCI6023E },
1430 { PCI_VDEVICE(NI, 0x2a70), BOARD_PCI6024E },
1431 { PCI_VDEVICE(NI, 0x2a80), BOARD_PCI6025E },
1432 { PCI_VDEVICE(NI, 0x2ab0), BOARD_PXI6025E },
1433 { PCI_VDEVICE(NI, 0x2b80), BOARD_PXI6713 },
1434 { PCI_VDEVICE(NI, 0x2b90), BOARD_PXI6711 },
1435 { PCI_VDEVICE(NI, 0x2c80), BOARD_PCI6035E },
1436 { PCI_VDEVICE(NI, 0x2ca0), BOARD_PCI6034E },
1437 { PCI_VDEVICE(NI, 0x70aa), BOARD_PCI6229 },
1438 { PCI_VDEVICE(NI, 0x70ab), BOARD_PCI6259 },
1439 { PCI_VDEVICE(NI, 0x70ac), BOARD_PCI6289 },
1440 { PCI_VDEVICE(NI, 0x70ad), BOARD_PXI6251 },
1441 { PCI_VDEVICE(NI, 0x70ae), BOARD_PXI6220 },
1442 { PCI_VDEVICE(NI, 0x70af), BOARD_PCI6221 },
1443 { PCI_VDEVICE(NI, 0x70b0), BOARD_PCI6220 },
1444 { PCI_VDEVICE(NI, 0x70b1), BOARD_PXI6229 },
1445 { PCI_VDEVICE(NI, 0x70b2), BOARD_PXI6259 },
1446 { PCI_VDEVICE(NI, 0x70b3), BOARD_PXI6289 },
1447 { PCI_VDEVICE(NI, 0x70b4), BOARD_PCI6250 },
1448 { PCI_VDEVICE(NI, 0x70b5), BOARD_PXI6221 },
1449 { PCI_VDEVICE(NI, 0x70b6), BOARD_PCI6280 },
1450 { PCI_VDEVICE(NI, 0x70b7), BOARD_PCI6254 },
1451 { PCI_VDEVICE(NI, 0x70b8), BOARD_PCI6251 },
1452 { PCI_VDEVICE(NI, 0x70b9), BOARD_PXI6250 },
1453 { PCI_VDEVICE(NI, 0x70ba), BOARD_PXI6254 },
1454 { PCI_VDEVICE(NI, 0x70bb), BOARD_PXI6280 },
1455 { PCI_VDEVICE(NI, 0x70bc), BOARD_PCI6284 },
1456 { PCI_VDEVICE(NI, 0x70bd), BOARD_PCI6281 },
1457 { PCI_VDEVICE(NI, 0x70be), BOARD_PXI6284 },
1458 { PCI_VDEVICE(NI, 0x70bf), BOARD_PXI6281 },
1459 { PCI_VDEVICE(NI, 0x70c0), BOARD_PCI6143 },
1460 { PCI_VDEVICE(NI, 0x70f2), BOARD_PCI6224 },
1461 { PCI_VDEVICE(NI, 0x70f3), BOARD_PXI6224 },
1462 { PCI_VDEVICE(NI, 0x710d), BOARD_PXI6143 },
1463 { PCI_VDEVICE(NI, 0x716c), BOARD_PCI6225 },
1464 { PCI_VDEVICE(NI, 0x716d), BOARD_PXI6225 },
1465 { PCI_VDEVICE(NI, 0x717d), BOARD_PCIE6251 },
1466 { PCI_VDEVICE(NI, 0x717f), BOARD_PCIE6259 },
1467 { PCI_VDEVICE(NI, 0x71bc), BOARD_PCI6221_37PIN },
1468 { PCI_VDEVICE(NI, 0x72e8), BOARD_PXIE6251 },
1469 { PCI_VDEVICE(NI, 0x72e9), BOARD_PXIE6259 },
1470 { 0 }
1471 };
1472 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1473
1474 static struct pci_driver ni_pcimio_pci_driver = {
1475 .name = "ni_pcimio",
1476 .id_table = ni_pcimio_pci_table,
1477 .probe = ni_pcimio_pci_probe,
1478 .remove = comedi_pci_auto_unconfig,
1479 };
1480 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1481
1482 MODULE_AUTHOR("Comedi https://www.comedi.org");
1483 MODULE_DESCRIPTION("Comedi low-level driver");
1484 MODULE_LICENSE("GPL");
1485