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/linux-6.12.1/include/vdso/
Dmath64.h36 #ifndef mul_u32_u32
37 static inline u64 mul_u32_u32(u32 a, u32 b) in mul_u32_u32() function
41 #define mul_u32_u32 mul_u32_u32 macro
49 ovf = __builtin_add_overflow(mul_u32_u32(al, mul), b, &ret); in mul_u64_u32_add_u64_shr()
54 ret += mul_u32_u32(ah, mul) << (32 - shift); in mul_u64_u32_add_u64_shr()
/linux-6.12.1/include/linux/
Dmath64.h151 #ifndef mul_u32_u32
155 static inline u64 mul_u32_u32(u32 a, u32 b) in mul_u32_u32() function
185 ret = mul_u32_u32(al, mul) >> shift; in mul_u64_u32_shr()
187 ret += mul_u32_u32(ah, mul) << (32 - shift); in mul_u64_u32_shr()
210 rl.ll = mul_u32_u32(a0.l.low, b0.l.low); in mul_u64_u64_shr()
211 rm.ll = mul_u32_u32(a0.l.low, b0.l.high); in mul_u64_u64_shr()
212 rn.ll = mul_u32_u32(a0.l.high, b0.l.low); in mul_u64_u64_shr()
213 rh.ll = mul_u32_u32(a0.l.high, b0.l.high); in mul_u64_u64_shr()
271 rl.ll = mul_u32_u32(u.l.low, mul); in mul_u64_u32_div()
272 rh.ll = mul_u32_u32(u.l.high, mul) + rl.l.high; in mul_u64_u32_div()
/linux-6.12.1/tools/include/linux/
Dmath64.h30 static inline u64 mul_u32_u32(u32 a, u32 b) in mul_u32_u32() function
40 static inline u64 mul_u32_u32(u32 a, u32 b) in mul_u32_u32() function
54 ret = mul_u32_u32(al, b) >> shift; in mul_u64_u32_shr()
56 ret += mul_u32_u32(ah, b) << (32 - shift); in mul_u64_u32_shr()
/linux-6.12.1/arch/x86/include/asm/
Ddiv64.h63 static inline u64 mul_u32_u32(u32 a, u32 b) in mul_u32_u32() function
72 #define mul_u32_u32 mul_u32_u32 macro
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_fixed.h79 tmp = mul_u32_u32(val, mul.val); in mul_round_up_u32_fixed16()
91 tmp = mul_u32_u32(val.val, mul.val); in mul_fixed16()
122 tmp = mul_u32_u32(val, mul.val); in mul_u32_fixed16()
Dintel_vrr.c149 crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal, in cmrr_get_vtotal()
151 vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n), in cmrr_get_vtotal()
153 adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m); in cmrr_get_vtotal()
Dintel_audio.c468 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
469 mul_u32_u32(link_clk, cdclk)); in calc_hblank_early_prog()
471 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000), in calc_hblank_early_prog()
472 mul_u32_u32(link_clk * lanes * 16, fec_coeff)); in calc_hblank_early_prog()
473 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), in calc_hblank_early_prog()
474 mul_u32_u32(64 * pixel_clk, 1000000)); in calc_hblank_early_prog()
Dintel_dp_mst.c85 return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72, in intel_dp_mst_max_dpt_bpp()
87 mul_u32_u32(adjusted_mode->crtc_clock, 1030000)); in intel_dp_mst_max_dpt_bpp()
135 m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n); in intel_dp_mst_compute_m_n()
444 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay, in mode_hblank_period_ns()
Dintel_vblank.c166 return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time, in intel_crtc_scanlines_since_frame_timestamp()
Dintel_fb.c1082 if (check_add_overflow(mul_u32_u32(height, fb->pitches[color_plane]), in intel_fb_offset_to_xy()
1657 if (mul_u32_u32(max_size, tile_size) > intel_bo_to_drm_bo(obj)->size) { in intel_fill_fb_info()
1660 mul_u32_u32(max_size, tile_size), intel_bo_to_drm_bo(obj)->size); in intel_fill_fb_info()
Dintel_crtc.c456 return DIV_ROUND_UP_ULL(mul_u32_u32(usecs, adjusted_mode->crtc_clock), in intel_usecs_to_scanlines()
/linux-6.12.1/drivers/gpu/drm/i915/selftests/
Di915_random.h49 return upper_32_bits(mul_u32_u32(prandom_u32_state(state), ep_ro)); in i915_prandom_u32_max_state()
/linux-6.12.1/include/drm/
Ddrm_color_mgmt.h46 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(user_input, (1 << bit_precision) - 1), in drm_color_lut_extract()
/linux-6.12.1/drivers/regulator/
Dmax5970-regulator.c287 div_u64(mul_u32_u32(data->shunt_micro_ohms, data->lim_uA), in max597x_set_ocp()
294 vthst = div_u64(mul_u32_u32(vthst, 120), 100); in max597x_set_ocp()
304 val = div_u64(mul_u32_u32(0xFF, vthfst), data->irng); in max597x_set_ocp()
/linux-6.12.1/drivers/acpi/
Dacpi_lpit.c108 lpit_native->counter_frequency : mul_u32_u32(tsc_khz, 1000U); in lpit_update_residency()
/linux-6.12.1/drivers/net/can/dev/
Dbittiming.c107 bt->tq = DIV_U64_ROUND_CLOSEST(mul_u32_u32(bt->brp, NSEC_PER_SEC), in can_fixup_bittiming()
/linux-6.12.1/drivers/gpu/drm/i915/gt/
Dintel_gt_clock_utils.c190 div_u64(mul_u32_u32(gt->clock_period_ns, S32_MAX), in intel_gt_init_clock_frequency()
Dintel_region_lmem.c250 mul_u32_u32(i915->params.lmem_size, SZ_1M)); in setup_lmem()
Dselftest_engine_cs.c126 sum = mul_u32_u32(a[2], 2); in trifilter()
Dselftest_migrate.c878 div64_u64(mul_u32_u32(4 * sz, in __perf_clear_blt()
961 div64_u64(mul_u32_u32(4 * sz, in __perf_copy_blt()
/linux-6.12.1/drivers/cpuidle/
Ddriver.c191 s->exit_latency_ns = mul_u32_u32(s->exit_latency, NSEC_PER_USEC); in __cpuidle_driver_init()
/linux-6.12.1/lib/
Ddhry_1.c289 return div_u64(mul_u32_u32(MSEC_PER_SEC, Number_Of_Runs), User_Time); in dhry()
/linux-6.12.1/drivers/gpu/drm/
Ddrm_rect.c65 tmp = mul_u32_u32(src, dst - *clip); in clip_scaled()
/linux-6.12.1/drivers/iio/light/
Dvcnl4000.c624 data->al_scale = div_u64(mul_u32_u32(data->chip_spec->ulux_step, in vcnl4040_write_als_it()
715 val_c = mul_u32_u32((*data->chip_spec->als_it_times)[it][1], in vcnl4040_read_als_period()
727 u64 val_n = mul_u32_u32(val, MICRO) + val2; in vcnl4040_write_als_period()
738 if (val_n < mul_u32_u32(vcnl4040_als_persistence[i], in vcnl4040_write_als_period()
/linux-6.12.1/drivers/gpu/drm/i915/gem/
Di915_gem_create.c203 args->size = mul_u32_u32(args->pitch, args->height); in i915_gem_dumb_create()

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