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Searched refs:mtk_phy_set_bits (Results 1 – 11 of 11) sorted by relevance

/linux-6.12.1/drivers/phy/mediatek/
Dphy-mtk-hdmi-mt2701.c55 mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); in mtk_hdmi_pll_prepare()
57 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); in mtk_hdmi_pll_prepare()
58 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); in mtk_hdmi_pll_prepare()
60 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN); in mtk_hdmi_pll_prepare()
61 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); in mtk_hdmi_pll_prepare()
62 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); in mtk_hdmi_pll_prepare()
64 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); in mtk_hdmi_pll_prepare()
65 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); in mtk_hdmi_pll_prepare()
66 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); in mtk_hdmi_pll_prepare()
67 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); in mtk_hdmi_pll_prepare()
[all …]
Dphy-mtk-hdmi-mt8195.c23 mtk_phy_set_bits(hdmi_phy->regs + HDMI_ANA_CTL, REG_ANA_HDMI20_FIFO_EN); in mtk_hdmi_ana_fifo_en()
59 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_BP2); in mtk_hdmi_pll_perf()
60 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BC); in mtk_hdmi_pll_perf()
64 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_BP); in mtk_hdmi_pll_perf()
70 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_1, RG_HDMITXPLL_RESERVE_BIT12_11); in mtk_hdmi_pll_perf()
71 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_0, RG_HDMITXPLL_TCL_EN); in mtk_hdmi_pll_perf()
100 mtk_phy_set_bits(regs + HDMI_1_CFG_3, RG_HDMITX21_SLDOLPF_EN); in mtk_hdmi_pll_set_hw()
102 mtk_phy_set_bits(regs + HDMI_1_PLL_CFG_2, RG_HDMITXPLL_PWD); in mtk_hdmi_pll_set_hw()
108 mtk_phy_set_bits(regs + HDMI_1_CFG_6, RG_HDMITX21_TX_POSDIV_EN); in mtk_hdmi_pll_set_hw()
202 mtk_phy_set_bits(regs + HDMI_CTL_3, REG_HDMITX_PIXEL_CLOCK); in mtk_hdmi_pll_set_hw()
[all …]
Dphy-mtk-ufs.c65 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON); in ufs_mtk_phy_set_active()
73 mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_PWR_ON); in ufs_mtk_phy_set_active()
81 mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN); in ufs_mtk_phy_set_active()
96 mtk_phy_set_bits(mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); in ufs_mtk_phy_set_deep_hibern()
99 mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); in ufs_mtk_phy_set_deep_hibern()
103 mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); in ufs_mtk_phy_set_deep_hibern()
104 mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_ISO_EN); in ufs_mtk_phy_set_deep_hibern()
107 mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); in ufs_mtk_phy_set_deep_hibern()
111 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); in ufs_mtk_phy_set_deep_hibern()
112 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN); in ufs_mtk_phy_set_deep_hibern()
[all …]
Dphy-mtk-mipi-dsi-mt8183.c77 mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); in mtk_mipi_tx_pll_enable()
84 mtk_phy_set_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); in mtk_mipi_tx_pll_enable()
96 mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); in mtk_mipi_tx_pll_disable()
154 mtk_phy_set_bits(base + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); in mtk_mipi_tx_power_on_signal()
163 mtk_phy_set_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_off_signal()
164 mtk_phy_set_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_off_signal()
165 mtk_phy_set_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_off_signal()
166 mtk_phy_set_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_off_signal()
167 mtk_phy_set_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); in mtk_mipi_tx_power_off_signal()
Dphy-mtk-hdmi-mt8173.c92 mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN); in mtk_hdmi_pll_prepare()
93 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV); in mtk_hdmi_pll_prepare()
95 mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN); in mtk_hdmi_pll_prepare()
97 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN); in mtk_hdmi_pll_prepare()
99 mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN); in mtk_hdmi_pll_prepare()
100 mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN); in mtk_hdmi_pll_prepare()
161 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV); in mtk_hdmi_pll_set_rate()
184 mtk_phy_set_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN); in mtk_hdmi_pll_set_rate()
232 mtk_phy_set_bits(hdmi_phy->regs + HDMI_CON3, in mtk_hdmi_phy_enable_tmds()
Dphy-mtk-tphy.c610 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL); in u3_phy_params_write()
615 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL); in u3_phy_params_write()
718 mtk_phy_set_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN); in hs_slew_rate_calibrate()
722 mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); in hs_slew_rate_calibrate()
734 mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); in hs_slew_rate_calibrate()
779 mtk_phy_set_bits(phyd + U3P_U3_PHYD_TOP1, P3D_RG_FORCE_PHY_MODE); in u3_phy_instance_init()
781 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD, in u3_phy_instance_init()
783 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE, in u3_phy_instance_init()
794 mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3, in u3_phy_instance_init()
833 mtk_phy_set_bits(com + U3P_U2PHYA_RESV1, in u2_phy_pll_26m_set()
[all …]
Dphy-mtk-mipi-dsi-mt8173.c173 mtk_phy_set_bits(base + MIPITX_DSI_CON, in mtk_mipi_tx_pll_prepare()
199 mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_FRA_EN); in mtk_mipi_tx_pll_prepare()
201 mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); in mtk_mipi_tx_pll_prepare()
261 mtk_phy_set_bits(mipi_tx->regs + reg, RG_DSI_LNTx_LDOOUT_EN); in mtk_mipi_tx_power_on_signal()
272 mtk_phy_set_bits(mipi_tx->regs + MIPITX_DSI_TOP_CON, in mtk_mipi_tx_power_off_signal()
Dphy-mtk-xfi-tphy.c169 mtk_phy_set_bits(xfi_tphy->base + 0x0030, 0xc00); in mtk_xfi_tphy_setup()
225 mtk_phy_set_bits(xfi_tphy->base + REG_ANA_GLB_D0, XTP_GLB_USXGMII_EN); in mtk_xfi_tphy_setup()
228 mtk_phy_set_bits(xfi_tphy->base + REG_DIG_GLB_70, in mtk_xfi_tphy_setup()
265 mtk_phy_set_bits(xfi_tphy->base + REG_DIG_LN_TRX_B0, XTP_LN_TX_MACCK_EN); in mtk_xfi_tphy_setup()
269 mtk_phy_set_bits(xfi_tphy->base + REG_DIG_LN_TRX_40, in mtk_xfi_tphy_setup()
Dphy-mtk-xsphy.c122 mtk_phy_set_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN); in u2_phy_slew_rate_calibrate()
126 mtk_phy_set_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); in u2_phy_slew_rate_calibrate()
133 mtk_phy_set_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); in u2_phy_slew_rate_calibrate()
175 mtk_phy_set_bits(pbase + XSP_USBPHYACR0, P2A0_RG_INTR_EN); in u2_phy_instance_init()
184 mtk_phy_set_bits(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN); in u2_phy_instance_power_on()
Dphy-mtk-io.h22 static inline void mtk_phy_set_bits(void __iomem *reg, u32 bits) in mtk_phy_set_bits() function
Dphy-mtk-mipi-csi-0-5.c136 mtk_phy_set_bits(base + MIPI_RX_ANA40_CSIXA, 0x90); in mtk_mipi_phy_power_on()