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Searched refs:mt7601u_rr (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/net/wireless/mediatek/mt7601u/
Dcore.c18 val = mt7601u_rr(dev, MT_MAC_CSR0); in mt7601u_wait_asic_ready()
38 cur = mt7601u_rr(dev, offset) & mask; in mt76_poll()
60 cur = mt7601u_rr(dev, offset) & mask; in mt76_poll_msec()
Dinit.c43 val = mt7601u_rr(dev, MT_CMB_CTRL); in mt7601u_set_wlan_state()
65 val = mt7601u_rr(dev, MT_WLAN_FUN_CTRL); in mt7601u_chip_onoff()
222 mt7601u_rr(dev, MT_RX_STA_CNT0); in mt7601u_reset_counters()
223 mt7601u_rr(dev, MT_RX_STA_CNT1); in mt7601u_reset_counters()
224 mt7601u_rr(dev, MT_RX_STA_CNT2); in mt7601u_reset_counters()
225 mt7601u_rr(dev, MT_TX_STA_CNT0); in mt7601u_reset_counters()
226 mt7601u_rr(dev, MT_TX_STA_CNT1); in mt7601u_reset_counters()
227 mt7601u_rr(dev, MT_TX_STA_CNT2); in mt7601u_reset_counters()
Deeprom.c150 val = mt7601u_rr(dev, MT_TX_ALC_CFG_0); in mt7601u_set_channel_power()
241 val = ((mt7601u_rr(dev, MT_TX_PWR_CFG_1) & 0x0000ff00) >> 8); in mt7601u_extra_power_over_mac()
242 val |= ((mt7601u_rr(dev, MT_TX_PWR_CFG_2) & 0x0000ff00) << 8); in mt7601u_extra_power_over_mac()
245 val = ((mt7601u_rr(dev, MT_TX_PWR_CFG_4) & 0x0000ff00) >> 8); in mt7601u_extra_power_over_mac()
Dusb.c145 u32 mt7601u_rr(struct mt7601u_dev *dev, u32 offset) in mt7601u_rr() function
295 asic_rev = mt7601u_rr(dev, MT_ASIC_VERSION); in mt7601u_probe()
296 mac_rev = mt7601u_rr(dev, MT_MAC_CSR0); in mt7601u_probe()
305 if (!(mt7601u_rr(dev, MT_EFUSE_CTRL) & MT_EFUSE_CTRL_SEL)) in mt7601u_probe()
Dphy.c78 val = mt7601u_rr(dev, MT_RF_CSR_CFG); in mt7601u_rf_rr()
167 val = mt7601u_rr(dev, MT_BBP_CSR_CFG); in mt7601u_bbp_rr()
498 rf_set = mt7601u_rr(dev, MT_RF_SETTING_0); in mt7601u_read_bootup_temp()
499 rf_bp = mt7601u_rr(dev, MT_RF_BYPASS_0); in mt7601u_read_bootup_temp()
559 mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL); in mt7601u_rxdc_cal()
939 val = mt7601u_rr(dev, MT_TX_ALC_CFG_1); in mt7601u_tssi_cal()
1132 mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL); in mt7601u_init_cal()
1193 old = mt7601u_rr(dev, MT_MAC_SYS_CTRL); in mt7601u_bbp_set_bw()
1230 dev->rf_pa_mode[0] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG0); in mt7601u_phy_init()
1231 dev->rf_pa_mode[1] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG1); in mt7601u_phy_init()
Dmac.c162 val = mt7601u_rr(dev, MT_TX_STAT_FIFO); in mt7601u_mac_fetch_tx_status()
269 u32 val = mt7601u_rr(dev, MT_BEACON_TIME_CFG); in mt7601u_mac_config_tsf()
289 u32 val = mt7601u_rr(dev, 0x10f4); in mt7601u_check_mac_err()
331 u32 val = mt7601u_rr(dev, spans[i].addr_base + j * 4); in mt7601u_mac_work()
559 val = mt7601u_rr(dev, MT_WCID_ATTR(idx)); in mt76_mac_wcid_set_key()
Dmt7601u.h283 u32 mt7601u_rr(struct mt7601u_dev *dev, u32 offset);
302 return mt7601u_rr(dev, offset); in mt76_rr()
Dmcu.c26 return mt7601u_rr(dev, MT_MCU_COM_REG0) == 1; in firmware_running()
328 val = mt7601u_rr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX); in __mt7601u_dma_fw()