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Searched refs:mmVM_L2_CNTL3 (Results 1 – 16 of 16) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v1_0.c205 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp); in gfxhub_v1_0_init_cache_regs()
367 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); in gfxhub_v1_0_gart_disable()
Dgmc_v6_0.c492 WREG32(mmVM_L2_CNTL3, in gmc_v6_0_gart_enable()
593 WREG32(mmVM_L2_CNTL3, in gmc_v6_0_gart_disable()
Dmmhub_v1_0.c191 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp); in mmhub_v1_0_init_cache_regs()
366 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0); in mmhub_v1_0_gart_disable()
Dgmc_v7_0.c635 tmp = RREG32(mmVM_L2_CNTL3); in gmc_v7_0_gart_enable()
639 WREG32(mmVM_L2_CNTL3, tmp); in gmc_v7_0_gart_enable()
Dgmc_v8_0.c851 tmp = RREG32(mmVM_L2_CNTL3); in gmc_v8_0_gart_enable()
855 WREG32(mmVM_L2_CNTL3, tmp); in gmc_v8_0_gart_enable()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_0_d.h543 #define mmVM_L2_CNTL3 0x502 macro
Dgmc_8_2_d.h601 #define mmVM_L2_CNTL3 0x502 macro
Dgmc_6_0_d.h1259 #define mmVM_L2_CNTL3 0x0502 macro
Dgmc_7_1_d.h576 #define mmVM_L2_CNTL3 0x502 macro
Dgmc_8_1_d.h599 #define mmVM_L2_CNTL3 0x502 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_9_3_0_offset.h1284 #define mmVM_L2_CNTL3 macro
Dmmhub_1_0_offset.h1268 #define mmVM_L2_CNTL3 macro
Dmmhub_9_1_offset.h1300 #define mmVM_L2_CNTL3 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h1169 #define mmVM_L2_CNTL3 macro
Dgc_9_1_offset.h1195 #define mmVM_L2_CNTL3 macro
Dgc_9_2_1_offset.h1133 #define mmVM_L2_CNTL3 macro