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Searched refs:mmVM_L2_CNTL (Results 1 – 16 of 16) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dmmhub_v1_0.c165 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); in mmhub_v1_0_init_cache_regs()
174 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); in mmhub_v1_0_init_cache_regs()
363 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); in mmhub_v1_0_gart_disable()
365 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); in mmhub_v1_0_gart_disable()
Dgfxhub_v1_0.c179 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); in gfxhub_v1_0_init_cache_regs()
188 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp); in gfxhub_v1_0_init_cache_regs()
Dgmc_v7_0.c621 tmp = RREG32(mmVM_L2_CNTL); in gmc_v7_0_gart_enable()
629 WREG32(mmVM_L2_CNTL, tmp); in gmc_v7_0_gart_enable()
739 tmp = RREG32(mmVM_L2_CNTL); in gmc_v7_0_gart_disable()
741 WREG32(mmVM_L2_CNTL, tmp); in gmc_v7_0_gart_disable()
Dgmc_v8_0.c836 tmp = RREG32(mmVM_L2_CNTL); in gmc_v8_0_gart_enable()
844 WREG32(mmVM_L2_CNTL, tmp); in gmc_v8_0_gart_enable()
971 tmp = RREG32(mmVM_L2_CNTL); in gmc_v8_0_gart_disable()
973 WREG32(mmVM_L2_CNTL, tmp); in gmc_v8_0_gart_disable()
Dgmc_v6_0.c480 WREG32(mmVM_L2_CNTL, in gmc_v6_0_gart_enable()
587 WREG32(mmVM_L2_CNTL, in gmc_v6_0_gart_disable()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_0_d.h541 #define mmVM_L2_CNTL 0x500 macro
Dgmc_8_2_d.h599 #define mmVM_L2_CNTL 0x500 macro
Dgmc_6_0_d.h1257 #define mmVM_L2_CNTL 0x0500 macro
Dgmc_7_1_d.h574 #define mmVM_L2_CNTL 0x500 macro
Dgmc_8_1_d.h597 #define mmVM_L2_CNTL 0x500 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_9_3_0_offset.h1280 #define mmVM_L2_CNTL … macro
Dmmhub_1_0_offset.h1264 #define mmVM_L2_CNTL … macro
Dmmhub_9_1_offset.h1296 #define mmVM_L2_CNTL … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h1165 #define mmVM_L2_CNTL … macro
Dgc_9_1_offset.h1191 #define mmVM_L2_CNTL … macro
Dgc_9_2_1_offset.h1129 #define mmVM_L2_CNTL … macro