Home
last modified time | relevance | path

Searched refs:mmVM_CONTEXT1_CNTL (Results 1 – 16 of 16) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgmc_v6_0.c385 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v6_0_set_fault_enable_default()
398 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v6_0_set_fault_enable_default()
533 WREG32(mmVM_CONTEXT1_CNTL, in gmc_v6_0_gart_enable()
581 WREG32(mmVM_CONTEXT1_CNTL, 0); in gmc_v6_0_gart_disable()
1037 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v6_0_vm_fault_interrupt_state()
1039 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v6_0_vm_fault_interrupt_state()
1045 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v6_0_vm_fault_interrupt_state()
1047 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v6_0_vm_fault_interrupt_state()
Dgmc_v7_0.c514 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_set_fault_enable_default()
527 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_set_fault_enable_default()
677 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_gart_enable()
682 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_gart_enable()
731 WREG32(mmVM_CONTEXT1_CNTL, 0); in gmc_v7_0_gart_disable()
1234 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1236 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
1244 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1246 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
Dgmc_v8_0.c727 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_set_fault_enable_default()
742 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_set_fault_enable_default()
908 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_gart_enable()
920 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_gart_enable()
963 WREG32(mmVM_CONTEXT1_CNTL, 0); in gmc_v8_0_gart_disable()
1396 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1398 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1406 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1408 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
Dgfxhub_v1_0.c265 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i * hub->ctx_distance); in gfxhub_v1_0_setup_vmid_config()
295 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, in gfxhub_v1_0_setup_vmid_config()
438 hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL; in gfxhub_v1_0_init()
Dmmhub_v1_0.c247 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i * hub->ctx_distance); in mmhub_v1_0_setup_vmid_config()
273 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, in mmhub_v1_0_setup_vmid_config()
441 hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL; in mmhub_v1_0_init()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_0_d.h546 #define mmVM_CONTEXT1_CNTL 0x505 macro
Dgmc_8_2_d.h604 #define mmVM_CONTEXT1_CNTL 0x505 macro
Dgmc_6_0_d.h1231 #define mmVM_CONTEXT1_CNTL 0x0505 macro
Dgmc_7_1_d.h579 #define mmVM_CONTEXT1_CNTL 0x505 macro
Dgmc_8_1_d.h602 #define mmVM_CONTEXT1_CNTL 0x505 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_9_3_0_offset.h1342 #define mmVM_CONTEXT1_CNTL … macro
Dmmhub_1_0_offset.h1326 #define mmVM_CONTEXT1_CNTL … macro
Dmmhub_9_1_offset.h1358 #define mmVM_CONTEXT1_CNTL … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h1234 #define mmVM_CONTEXT1_CNTL … macro
Dgc_9_1_offset.h1253 #define mmVM_CONTEXT1_CNTL … macro
Dgc_9_2_1_offset.h1191 #define mmVM_CONTEXT1_CNTL … macro