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Searched refs:mmVM_CONTEXT0_CNTL (Results 1 – 17 of 17) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v1_0.c222 tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); in gfxhub_v1_0_enable_system_domain()
230 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); in gfxhub_v1_0_enable_system_domain()
349 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, in gfxhub_v1_0_gart_disable()
432 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL); in gfxhub_v1_0_init()
438 hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL; in gfxhub_v1_0_init()
Dgmc_v6_0.c503 WREG32(mmVM_CONTEXT0_CNTL, in gmc_v6_0_gart_enable()
580 WREG32(mmVM_CONTEXT0_CNTL, 0); in gmc_v6_0_gart_disable()
1034 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v6_0_vm_fault_interrupt_state()
1036 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v6_0_vm_fault_interrupt_state()
1042 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v6_0_vm_fault_interrupt_state()
1044 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v6_0_vm_fault_interrupt_state()
Dmmhub_v1_0.c203 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); in mmhub_v1_0_enable_system_domain()
208 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp); in mmhub_v1_0_enable_system_domain()
349 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, in mmhub_v1_0_gart_disable()
435 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL); in mmhub_v1_0_init()
441 hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL; in mmhub_v1_0_init()
Dgmc_v7_0.c647 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v7_0_gart_enable()
651 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v7_0_gart_enable()
730 WREG32(mmVM_CONTEXT0_CNTL, 0); in gmc_v7_0_gart_disable()
1230 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1232 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
1240 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1242 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
Dgmc_v8_0.c878 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v8_0_gart_enable()
882 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_gart_enable()
962 WREG32(mmVM_CONTEXT0_CNTL, 0); in gmc_v8_0_gart_disable()
1392 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1394 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1402 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1404 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
Dsi.c91 mmVM_CONTEXT0_CNTL, 0x20000000, 0x20fffed8,
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_0_d.h545 #define mmVM_CONTEXT0_CNTL 0x504 macro
Dgmc_8_2_d.h603 #define mmVM_CONTEXT0_CNTL 0x504 macro
Dgmc_6_0_d.h1217 #define mmVM_CONTEXT0_CNTL 0x0504 macro
Dgmc_7_1_d.h578 #define mmVM_CONTEXT0_CNTL 0x504 macro
Dgmc_8_1_d.h601 #define mmVM_CONTEXT0_CNTL 0x504 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_9_3_0_offset.h1340 #define mmVM_CONTEXT0_CNTL macro
Dmmhub_1_0_offset.h1324 #define mmVM_CONTEXT0_CNTL macro
Dmmhub_9_1_offset.h1356 #define mmVM_CONTEXT0_CNTL macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h1232 #define mmVM_CONTEXT0_CNTL macro
Dgc_9_1_offset.h1251 #define mmVM_CONTEXT0_CNTL macro
Dgc_9_2_1_offset.h1189 #define mmVM_CONTEXT0_CNTL macro