| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 93 #define mmUVD_VCPU_CACHE_SIZE2 0x3D3B macro
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| D | uvd_4_2_d.h | 65 #define mmUVD_VCPU_CACHE_SIZE2 0x3d87 macro
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| D | uvd_3_1_d.h | 67 #define mmUVD_VCPU_CACHE_SIZE2 0x3d87 macro
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| D | uvd_5_0_d.h | 71 #define mmUVD_VCPU_CACHE_SIZE2 0x3d87 macro
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| D | uvd_6_0_d.h | 87 #define mmUVD_VCPU_CACHE_SIZE2 0x3d87 macro
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| D | uvd_7_0_offset.h | 188 #define mmUVD_VCPU_CACHE_SIZE2 … macro
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 374 #define mmUVD_VCPU_CACHE_SIZE2 … macro
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| D | vcn_2_5_offset.h | 695 #define mmUVD_VCPU_CACHE_SIZE2 … macro
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| D | vcn_2_0_0_offset.h | 624 #define mmUVD_VCPU_CACHE_SIZE2 … macro
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| D | vcn_3_0_0_offset.h | 1071 #define mmUVD_VCPU_CACHE_SIZE2 … macro
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v3_1.c | 260 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); in uvd_v3_1_mc_resume()
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| D | uvd_v4_2.c | 594 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); in uvd_v4_2_mc_resume()
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| D | vcn_v2_0.c | 417 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_0_mc_resume()
507 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1990 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), in vcn_v2_0_start_sriov()
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| D | uvd_v5_0.c | 306 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); in uvd_v5_0_mc_resume()
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| D | vcn_v2_5.c | 504 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_5_mc_resume()
593 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1350 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2), in vcn_v2_5_sriov_start()
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| D | vcn_v3_0.c | 531 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v3_0_mc_resume()
619 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1434 mmUVD_VCPU_CACHE_SIZE2), in vcn_v3_0_start_sriov()
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| D | uvd_v7_0.c | 717 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, in uvd_v7_0_mc_resume()
860 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), in uvd_v7_0_sriov_start()
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| D | vcn_v1_0.c | 385 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v1_0_mc_resume_spg_mode()
459 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, in vcn_v1_0_mc_resume_dpg_mode()
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| D | uvd_v6_0.c | 630 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); in uvd_v6_0_mc_resume()
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