| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 90 #define mmUVD_VCPU_CACHE_OFFSET2 0x3D3A macro
|
| D | uvd_4_2_d.h | 64 #define mmUVD_VCPU_CACHE_OFFSET2 0x3d86 macro
|
| D | uvd_3_1_d.h | 66 #define mmUVD_VCPU_CACHE_OFFSET2 0x3d86 macro
|
| D | uvd_5_0_d.h | 70 #define mmUVD_VCPU_CACHE_OFFSET2 0x3d86 macro
|
| D | uvd_6_0_d.h | 86 #define mmUVD_VCPU_CACHE_OFFSET2 0x3d86 macro
|
| D | uvd_7_0_offset.h | 186 #define mmUVD_VCPU_CACHE_OFFSET2 … macro
|
| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 372 #define mmUVD_VCPU_CACHE_OFFSET2 … macro
|
| D | vcn_2_5_offset.h | 693 #define mmUVD_VCPU_CACHE_OFFSET2 … macro
|
| D | vcn_2_0_0_offset.h | 622 #define mmUVD_VCPU_CACHE_OFFSET2 … macro
|
| D | vcn_3_0_0_offset.h | 1069 #define mmUVD_VCPU_CACHE_OFFSET2 … macro
|
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v3_1.c | 259 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); in uvd_v3_1_mc_resume()
|
| D | uvd_v4_2.c | 593 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); in uvd_v4_2_mc_resume()
|
| D | vcn_v2_0.c | 416 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v2_0_mc_resume()
505 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1987 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), in vcn_v2_0_start_sriov()
|
| D | uvd_v5_0.c | 305 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); in uvd_v5_0_mc_resume()
|
| D | vcn_v2_5.c | 503 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v2_5_mc_resume()
591 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1347 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2), in vcn_v2_5_sriov_start()
|
| D | vcn_v3_0.c | 530 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v3_0_mc_resume()
617 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1431 mmUVD_VCPU_CACHE_OFFSET2), in vcn_v3_0_start_sriov()
|
| D | uvd_v7_0.c | 716 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21)); in uvd_v7_0_mc_resume()
859 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21)); in uvd_v7_0_sriov_start()
|
| D | vcn_v1_0.c | 384 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v1_0_mc_resume_spg_mode()
458 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
|
| D | uvd_v6_0.c | 629 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); in uvd_v6_0_mc_resume()
|