| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 88 #define mmUVD_VCPU_CACHE_OFFSET0 0x3D36 macro
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| D | uvd_4_2_d.h | 60 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
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| D | uvd_3_1_d.h | 62 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
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| D | uvd_5_0_d.h | 66 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
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| D | uvd_6_0_d.h | 82 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
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| D | uvd_7_0_offset.h | 178 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v2_5.c | 477 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
485 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_5_mc_resume()
532 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
539 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
551 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_5_mc_resume_dpg_mode()
1303 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0); in vcn_v2_5_sriov_start()
1315 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_5_sriov_start()
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| D | vcn_v3_0.c | 504 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v3_0_mc_resume()
512 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v3_0_mc_resume()
558 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
565 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
577 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_mc_resume_dpg_mode()
1389 mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_start_sriov()
1400 mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_start_sriov()
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| D | vcn_v2_0.c | 389 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_0_mc_resume()
397 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_0_mc_resume()
446 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
453 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
465 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_0_mc_resume_dpg_mode()
1955 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_0_start_sriov()
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| D | uvd_v7_0.c | 691 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in uvd_v7_0_mc_resume()
699 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, in uvd_v7_0_mc_resume()
833 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); in uvd_v7_0_sriov_start()
841 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), in uvd_v7_0_sriov_start()
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| D | vcn_v1_0.c | 357 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v1_0_mc_resume_spg_mode()
365 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v1_0_mc_resume_spg_mode()
426 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, in vcn_v1_0_mc_resume_dpg_mode()
435 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v1_0_mc_resume_dpg_mode()
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| D | uvd_v3_1.c | 248 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); in uvd_v3_1_mc_resume()
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| D | uvd_v4_2.c | 582 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); in uvd_v4_2_mc_resume()
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| D | uvd_v5_0.c | 294 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); in uvd_v5_0_mc_resume()
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| D | uvd_v6_0.c | 618 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); in uvd_v6_0_mc_resume()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 364 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
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| D | vcn_2_5_offset.h | 685 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
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| D | vcn_2_0_0_offset.h | 614 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
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| D | vcn_3_0_0_offset.h | 1061 #define mmUVD_VCPU_CACHE_OFFSET0 … macro
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