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Searched refs:mmUVD_UDEC_DB_ADDR_CONFIG (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h86 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3BD4 macro
Duvd_4_2_d.h35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 macro
Duvd_3_1_d.h35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 macro
Duvd_5_0_d.h35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 macro
Duvd_6_0_d.h35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 macro
Duvd_7_0_offset.h62 #define mmUVD_UDEC_DB_ADDR_CONFIG macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h150 #define mmUVD_UDEC_DB_ADDR_CONFIG macro
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c271 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v3_1_mc_resume()
Duvd_v4_2.c605 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v4_2_mc_resume()
Duvd_v5_0.c309 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v5_0_mc_resume()
Dvcn_v1_0.c389 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, in vcn_v1_0_mc_resume_spg_mode()
465 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, in vcn_v1_0_mc_resume_dpg_mode()
Duvd_v6_0.c633 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v6_0_mc_resume()
Duvd_v7_0.c722 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG, in uvd_v7_0_mc_resume()
Dgfx_v6_0.c1707 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in gfx_v6_0_constants_init()