/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
D | uvd_v3_1.c | 331 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v3_1_start() 385 status = RREG32(mmUVD_STATUS); in uvd_v3_1_start() 411 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v3_1_start() 456 status = RREG32(mmUVD_STATUS); in uvd_v3_1_stop() 499 WREG32(mmUVD_STATUS, 0); in uvd_v3_1_stop() 701 if (RREG32(mmUVD_STATUS) != 0) in uvd_v3_1_hw_fini()
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D | uvd_v4_2.c | 215 if (RREG32(mmUVD_STATUS) != 0) in uvd_v4_2_hw_fini() 294 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start() 348 status = RREG32(mmUVD_STATUS); in uvd_v4_2_start() 374 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v4_2_start() 419 status = RREG32(mmUVD_STATUS); in uvd_v4_2_stop() 462 WREG32(mmUVD_STATUS, 0); in uvd_v4_2_stop()
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D | uvd_v5_0.c | 213 if (RREG32(mmUVD_STATUS) != 0) in uvd_v5_0_hw_fini() 392 status = RREG32(mmUVD_STATUS); in uvd_v5_0_start() 418 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start() 480 WREG32(mmUVD_STATUS, 0); in uvd_v5_0_stop()
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D | vcn_v1_0.c | 50 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), 283 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) { in vcn_v1_0_hw_fini() 842 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode() 843 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode() 914 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v1_0_start_spg_mode() 948 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode() 949 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode() 1165 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v1_0_stop_spg_mode() 1200 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); in vcn_v1_0_stop_spg_mode() 1384 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v1_0_is_idle() [all …]
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D | vcn_v2_0.c | 58 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), 320 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) in vcn_v2_0_hw_fini() 991 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v2_0_start() 992 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v2_0_start() 1066 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v2_0_start() 1097 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, in vcn_v2_0_start() 1190 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_0_stop() 1233 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); in vcn_v2_0_stop() 1326 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_0_is_idle() 1334 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_0_wait_for_idle() [all …]
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D | vcn_v3_0.c | 65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), 434 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { in vcn_v3_0_hw_fini() 1162 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v3_0_start() 1163 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v3_0_start() 1237 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v3_0_start() 1269 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v3_0_start() 1375 mmUVD_STATUS), in vcn_v3_0_start_sriov() 1583 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v3_0_stop() 1628 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); in vcn_v3_0_stop() 2113 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v3_0_is_idle() [all …]
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D | vcn_v2_5.c | 61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), 401 RREG32_SOC15(VCN, i, mmUVD_STATUS))) in vcn_v2_5_hw_fini() 1033 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v2_5_start() 1034 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v2_5_start() 1117 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v2_5_start() 1152 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v2_5_start() 1287 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), in vcn_v2_5_sriov_start() 1442 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop() 1480 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); in vcn_v2_5_stop() 1783 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_5_is_idle() [all …]
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D | uvd_v6_0.c | 537 if (RREG32(mmUVD_STATUS) != 0) in uvd_v6_0_hw_fini() 807 status = RREG32(mmUVD_STATUS); in uvd_v6_0_start() 834 WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); in uvd_v6_0_start() 911 WREG32(mmUVD_STATUS, 0); in uvd_v6_0_stop() 1175 (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK)) in uvd_v6_0_check_soft_reset()
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D | uvd_v7_0.c | 823 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start() 913 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start() 935 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02); in uvd_v7_0_sriov_start() 1050 status = RREG32_SOC15(UVD, k, mmUVD_STATUS); in uvd_v7_0_start() 1080 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, in uvd_v7_0_start() 1495 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
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/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
D | uvd_4_0_d.h | 84 #define mmUVD_STATUS 0x3DAF macro
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D | uvd_4_2_d.h | 76 #define mmUVD_STATUS 0x3daf macro
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D | uvd_3_1_d.h | 78 #define mmUVD_STATUS 0x3daf macro
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D | uvd_5_0_d.h | 82 #define mmUVD_STATUS 0x3daf macro
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D | uvd_6_0_d.h | 98 #define mmUVD_STATUS 0x3daf macro
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D | uvd_7_0_offset.h | 208 #define mmUVD_STATUS … macro
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/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
D | vcn_1_0_offset.h | 394 #define mmUVD_STATUS … macro
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D | vcn_2_5_offset.h | 487 #define mmUVD_STATUS … macro
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D | vcn_2_0_0_offset.h | 698 #define mmUVD_STATUS … macro
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D | vcn_3_0_0_offset.h | 797 #define mmUVD_STATUS … macro
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