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Searched refs:mmUVD_SOFT_RESET (Results 1 – 18 of 18) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c374 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v3_1_start()
376 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v3_1_start()
378 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v3_1_start()
395 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v3_1_start()
398 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v3_1_start()
495 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | in uvd_v3_1_stop()
Duvd_v4_2.c337 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v4_2_start()
339 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v4_2_start()
341 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
358 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v4_2_start()
361 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
458 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | in uvd_v4_2_stop()
Duvd_v5_0.c345 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | in uvd_v5_0_start()
376 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_start()
386 WREG32(mmUVD_SOFT_RESET, 0); in uvd_v5_0_start()
402 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v5_0_start()
405 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_start()
471 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_stop()
Duvd_v7_0.c880 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), in uvd_v7_0_sriov_start()
900 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), in uvd_v7_0_sriov_start()
929 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0); in uvd_v7_0_sriov_start()
994 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, in uvd_v7_0_start()
1030 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, in uvd_v7_0_start()
1043 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); in uvd_v7_0_start()
1060 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), in uvd_v7_0_start()
1064 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, in uvd_v7_0_start()
1157 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET, in uvd_v7_0_stop()
Dvcn_v1_0.c898 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v1_0_start_spg_mode()
905 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); in vcn_v1_0_start_spg_mode()
908 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); in vcn_v1_0_start_spg_mode()
924 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_start_spg_mode()
928 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v1_0_start_spg_mode()
1077 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); in vcn_v1_0_start_dpg_mode()
1187 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_stop_spg_mode()
1191 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_stop_spg_mode()
1196 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_stop_spg_mode()
Dvcn_v2_0.c915 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect); in vcn_v2_0_start_dpg_mode()
1042 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v2_0_start()
1049 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); in vcn_v2_0_start()
1052 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); in vcn_v2_0_start()
1076 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_start()
1080 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v2_0_start()
1218 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_stop()
1223 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_stop()
1228 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_stop()
Duvd_v6_0.c750 WREG32(mmUVD_SOFT_RESET, in uvd_v6_0_start()
790 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v6_0_start()
800 WREG32(mmUVD_SOFT_RESET, 0); in uvd_v6_0_start()
902 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v6_0_stop()
Dvcn_v3_0.c1180 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_start()
1183 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); in vcn_v3_0_start()
1620 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_stop()
1622 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); in vcn_v3_0_stop()
1623 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_stop()
1625 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); in vcn_v3_0_stop()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h83 #define mmUVD_SOFT_RESET 0x3DA0 macro
Duvd_4_2_d.h67 #define mmUVD_SOFT_RESET 0x3da0 macro
Duvd_3_1_d.h69 #define mmUVD_SOFT_RESET 0x3da0 macro
Duvd_5_0_d.h73 #define mmUVD_SOFT_RESET 0x3da0 macro
Duvd_6_0_d.h89 #define mmUVD_SOFT_RESET 0x3da0 macro
Duvd_7_0_offset.h192 #define mmUVD_SOFT_RESET … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h378 #define mmUVD_SOFT_RESET … macro
Dvcn_2_5_offset.h491 #define mmUVD_SOFT_RESET … macro
Dvcn_2_0_0_offset.h672 #define mmUVD_SOFT_RESET … macro
Dvcn_3_0_0_offset.h805 #define mmUVD_SOFT_RESET … macro