Searched refs:mmUVD_RBC_RB_WPTR_CNTL (Results 1 – 19 of 19) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 74 #define mmUVD_RBC_RB_WPTR_CNTL 0x3DA6 macro
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| D | uvd_4_2_d.h | 73 #define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 macro
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| D | uvd_3_1_d.h | 75 #define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 macro
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| D | uvd_5_0_d.h | 79 #define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 macro
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| D | uvd_6_0_d.h | 95 #define mmUVD_RBC_RB_WPTR_CNTL 0x3da6 macro
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| D | uvd_7_0_offset.h | 202 #define mmUVD_RBC_RB_WPTR_CNTL … macro
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 388 #define mmUVD_RBC_RB_WPTR_CNTL … macro
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| D | vcn_2_5_offset.h | 797 #define mmUVD_RBC_RB_WPTR_CNTL … macro
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| D | vcn_2_0_0_offset.h | 684 #define mmUVD_RBC_RB_WPTR_CNTL … macro
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| D | vcn_3_0_0_offset.h | 1183 #define mmUVD_RBC_RB_WPTR_CNTL … macro
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v3_1.c | 417 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); in uvd_v3_1_start()
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| D | uvd_v4_2.c | 380 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); in uvd_v4_2_start()
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| D | uvd_v5_0.c | 432 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); in uvd_v5_0_start()
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| D | vcn_v1_0.c | 961 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); in vcn_v1_0_start_spg_mode()
1119 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); in vcn_v1_0_start_dpg_mode()
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| D | uvd_v6_0.c | 847 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); in uvd_v6_0_start()
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| D | uvd_v7_0.c | 1094 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0); in uvd_v7_0_start()
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| D | vcn_v2_0.c | 946 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); in vcn_v2_0_start_dpg_mode()
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| D | vcn_v2_5.c | 982 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); in vcn_v2_5_start_dpg_mode()
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| D | vcn_v3_0.c | 1104 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); in vcn_v3_0_start_dpg_mode()
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