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Searched refs:mmUVD_RBC_RB_RPTR_ADDR (Results 1 – 17 of 17) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h72 #define mmUVD_RBC_RB_RPTR_ADDR 0x3DAA macro
Duvd_4_2_d.h75 #define mmUVD_RBC_RB_RPTR_ADDR 0x3daa macro
Duvd_3_1_d.h77 #define mmUVD_RBC_RB_RPTR_ADDR 0x3daa macro
Duvd_5_0_d.h81 #define mmUVD_RBC_RB_RPTR_ADDR 0x3daa macro
Duvd_6_0_d.h97 #define mmUVD_RBC_RB_RPTR_ADDR 0x3daa macro
Duvd_7_0_offset.h206 #define mmUVD_RBC_RB_RPTR_ADDR macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h392 #define mmUVD_RBC_RB_RPTR_ADDR macro
Dvcn_2_5_offset.h787 #define mmUVD_RBC_RB_RPTR_ADDR macro
Dvcn_2_0_0_offset.h692 #define mmUVD_RBC_RB_RPTR_ADDR macro
Dvcn_3_0_0_offset.h1171 #define mmUVD_RBC_RB_RPTR_ADDR macro
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c435 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); in uvd_v5_0_start()
Dvcn_v1_0.c964 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, in vcn_v1_0_start_spg_mode()
1122 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, in vcn_v1_0_start_dpg_mode()
Duvd_v6_0.c850 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); in uvd_v6_0_start()
Duvd_v7_0.c1097 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR, in uvd_v7_0_start()
Dvcn_v2_0.c949 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, in vcn_v2_0_start_dpg_mode()
Dvcn_v2_5.c985 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, in vcn_v2_5_start_dpg_mode()
Dvcn_v3_0.c1107 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, in vcn_v3_0_start_dpg_mode()