Home
last modified time | relevance | path

Searched refs:mmUVD_RBC_RB_RPTR (Results 1 – 19 of 19) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h71 #define mmUVD_RBC_RB_RPTR 0x3DA4 macro
Duvd_4_2_d.h71 #define mmUVD_RBC_RB_RPTR 0x3da4 macro
Duvd_3_1_d.h73 #define mmUVD_RBC_RB_RPTR 0x3da4 macro
Duvd_5_0_d.h77 #define mmUVD_RBC_RB_RPTR 0x3da4 macro
Duvd_6_0_d.h93 #define mmUVD_RBC_RB_RPTR 0x3da4 macro
Duvd_7_0_offset.h198 #define mmUVD_RBC_RB_RPTR … macro
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c48 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v3_1_ring_get_rptr()
424 WREG32(mmUVD_RBC_RB_RPTR, 0x0); in uvd_v3_1_start()
426 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); in uvd_v3_1_start()
Duvd_v4_2.c62 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v4_2_ring_get_rptr()
387 WREG32(mmUVD_RBC_RB_RPTR, 0x0); in uvd_v4_2_start()
389 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); in uvd_v4_2_start()
Duvd_v5_0.c60 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v5_0_ring_get_rptr()
444 WREG32(mmUVD_RBC_RB_RPTR, 0); in uvd_v5_0_start()
446 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); in uvd_v5_0_start()
Dvcn_v3_0.c1117 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); in vcn_v3_0_start_dpg_mode()
1121 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); in vcn_v3_0_start_dpg_mode()
1294 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); in vcn_v3_0_start()
1297 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); in vcn_v3_0_start()
1556 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1702 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); in vcn_v3_0_pause_dpg_mode()
1735 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); in vcn_v3_0_dec_ring_get_rptr()
Dvcn_v1_0.c974 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); in vcn_v1_0_start_spg_mode()
978 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v1_0_start_spg_mode()
1132 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); in vcn_v1_0_start_dpg_mode()
1136 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v1_0_start_dpg_mode()
1227 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
1427 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v1_0_dec_ring_get_rptr()
Dvcn_v2_0.c959 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_0_start_dpg_mode()
963 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v2_0_start_dpg_mode()
1119 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_0_start()
1121 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v2_0_start()
1165 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1372 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v2_0_dec_ring_get_rptr()
Dvcn_v2_5.c995 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_5_start_dpg_mode()
999 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); in vcn_v2_5_start_dpg_mode()
1175 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_5_start()
1177 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); in vcn_v2_5_start()
1416 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1582 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); in vcn_v2_5_dec_ring_get_rptr()
Duvd_v6_0.c81 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v6_0_ring_get_rptr()
859 WREG32(mmUVD_RBC_RB_RPTR, 0); in uvd_v6_0_start()
861 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); in uvd_v6_0_start()
Duvd_v7_0.c75 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); in uvd_v7_0_ring_get_rptr()
1107 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0); in uvd_v7_0_start()
1109 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); in uvd_v7_0_start()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h384 #define mmUVD_RBC_RB_RPTR … macro
Dvcn_2_5_offset.h789 #define mmUVD_RBC_RB_RPTR … macro
Dvcn_2_0_0_offset.h680 #define mmUVD_RBC_RB_RPTR … macro
Dvcn_3_0_0_offset.h1173 #define mmUVD_RBC_RB_RPTR … macro