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Searched refs:mmUVD_RBC_RB_CNTL (Results 1 – 19 of 19) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h70 #define mmUVD_RBC_RB_CNTL 0x3DA9 macro
Duvd_4_2_d.h74 #define mmUVD_RBC_RB_CNTL 0x3da9 macro
Duvd_3_1_d.h76 #define mmUVD_RBC_RB_CNTL 0x3da9 macro
Duvd_5_0_d.h80 #define mmUVD_RBC_RB_CNTL 0x3da9 macro
Duvd_6_0_d.h96 #define mmUVD_RBC_RB_CNTL 0x3da9 macro
Duvd_7_0_offset.h204 #define mmUVD_RBC_RB_CNTL macro
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c414 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v3_1_start()
435 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v3_1_start()
452 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v3_1_stop()
Duvd_v4_2.c377 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v4_2_start()
398 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
415 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v4_2_stop()
Duvd_v5_0.c429 WREG32(mmUVD_RBC_RB_CNTL, tmp); in uvd_v5_0_start()
449 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); in uvd_v5_0_start()
464 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v5_0_stop()
Duvd_v7_0.c920 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); in uvd_v7_0_sriov_start()
1091 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp); in uvd_v7_0_start()
1113 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, in uvd_v7_0_start()
1148 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v7_0_stop()
Dvcn_v1_0.c958 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); in vcn_v1_0_start_spg_mode()
982 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, in vcn_v1_0_start_spg_mode()
1116 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); in vcn_v1_0_start_dpg_mode()
1140 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, in vcn_v1_0_start_dpg_mode()
Dvcn_v2_0.c937 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_0_start_dpg_mode()
1109 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_0_start()
2025 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); in vcn_v2_0_start_sriov()
Duvd_v6_0.c844 WREG32(mmUVD_RBC_RB_CNTL, tmp); in uvd_v6_0_start()
895 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); in uvd_v6_0_stop()
Dvcn_v2_5.c973 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_5_start_dpg_mode()
1165 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_5_start()
1385 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp); in vcn_v2_5_sriov_start()
Dvcn_v3_0.c1095 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); in vcn_v3_0_start_dpg_mode()
1282 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); in vcn_v3_0_start()
1469 mmUVD_RBC_RB_CNTL), in vcn_v3_0_start_sriov()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h390 #define mmUVD_RBC_RB_CNTL macro
Dvcn_2_5_offset.h785 #define mmUVD_RBC_RB_CNTL macro
Dvcn_2_0_0_offset.h690 #define mmUVD_RBC_RB_CNTL macro
Dvcn_3_0_0_offset.h1169 #define mmUVD_RBC_RB_CNTL macro