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Searched refs:mmUVD_MPC_SET_MUXB0 (Results 1 – 19 of 19) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h58 #define mmUVD_MPC_SET_MUXB0 0x3D7B macro
Duvd_4_2_d.h56 #define mmUVD_MPC_SET_MUXB0 0x3d7b macro
Duvd_3_1_d.h58 #define mmUVD_MPC_SET_MUXB0 0x3d7b macro
Duvd_5_0_d.h62 #define mmUVD_MPC_SET_MUXB0 0x3d7b macro
Duvd_6_0_d.h78 #define mmUVD_MPC_SET_MUXB0 0x3d7b macro
Duvd_7_0_offset.h170 #define mmUVD_MPC_SET_MUXB0 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h350 #define mmUVD_MPC_SET_MUXB0 macro
Dvcn_2_5_offset.h765 #define mmUVD_MPC_SET_MUXB0 macro
Dvcn_2_0_0_offset.h600 #define mmUVD_MPC_SET_MUXB0 macro
Dvcn_3_0_0_offset.h1145 #define mmUVD_MPC_SET_MUXB0 macro
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c363 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); in uvd_v3_1_start()
Duvd_v4_2.c324 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); in uvd_v4_2_start()
Duvd_v5_0.c370 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); in uvd_v5_0_start()
Dvcn_v1_0.c877 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, in vcn_v1_0_start_spg_mode()
1060 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0, in vcn_v1_0_start_dpg_mode()
Dvcn_v2_0.c894 UVD, 0, mmUVD_MPC_SET_MUXB0), in vcn_v2_0_start_dpg_mode()
1027 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, in vcn_v2_0_start()
Dvcn_v2_5.c923 VCN, 0, mmUVD_MPC_SET_MUXB0), in vcn_v2_5_start_dpg_mode()
1077 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, in vcn_v2_5_start()
Dvcn_v3_0.c1043 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), in vcn_v3_0_start_dpg_mode()
1207 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, in vcn_v3_0_start()
Duvd_v6_0.c784 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); in uvd_v6_0_start()
Duvd_v7_0.c1024 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040); in uvd_v7_0_start()