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Searched refs:mmUVD_MPC_SET_MUXA1 (Results 1 – 15 of 15) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h57 #define mmUVD_MPC_SET_MUXA1 0x3D7A macro
Duvd_4_2_d.h55 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
Duvd_3_1_d.h57 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
Duvd_5_0_d.h61 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
Duvd_6_0_d.h77 #define mmUVD_MPC_SET_MUXA1 0x3d7a macro
Duvd_7_0_offset.h168 #define mmUVD_MPC_SET_MUXA1 … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h348 #define mmUVD_MPC_SET_MUXA1 … macro
Dvcn_2_5_offset.h763 #define mmUVD_MPC_SET_MUXA1 … macro
Dvcn_2_0_0_offset.h598 #define mmUVD_MPC_SET_MUXA1 … macro
Dvcn_3_0_0_offset.h1143 #define mmUVD_MPC_SET_MUXA1 … macro
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c362 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v3_1_start()
Duvd_v4_2.c323 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v4_2_start()
Duvd_v5_0.c369 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v5_0_start()
Duvd_v6_0.c783 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v6_0_start()
Duvd_v7_0.c1023 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0); in uvd_v7_0_start()