Searched refs:mmUVD_MPC_CNTL (Results 1 – 15 of 15) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 53 #define mmUVD_MPC_CNTL 0x3D77 macro
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| D | uvd_4_2_d.h | 53 #define mmUVD_MPC_CNTL 0x3d77 macro
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| D | uvd_3_1_d.h | 55 #define mmUVD_MPC_CNTL 0x3d77 macro
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| D | uvd_5_0_d.h | 59 #define mmUVD_MPC_CNTL 0x3d77 macro
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| D | uvd_6_0_d.h | 75 #define mmUVD_MPC_CNTL 0x3d77 macro
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v3_1.c | 358 tmp = RREG32(mmUVD_MPC_CNTL); in uvd_v3_1_start()
359 WREG32(mmUVD_MPC_CNTL, tmp | 0x10); in uvd_v3_1_start()
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| D | uvd_v4_2.c | 319 tmp = RREG32(mmUVD_MPC_CNTL); in uvd_v4_2_start()
320 WREG32(mmUVD_MPC_CNTL, tmp | 0x10); in uvd_v4_2_start()
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| D | vcn_v1_0.c | 866 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); in vcn_v1_0_start_spg_mode()
869 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); in vcn_v1_0_start_spg_mode()
1051 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL, in vcn_v1_0_start_dpg_mode()
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| D | vcn_v2_0.c | 883 UVD, 0, mmUVD_MPC_CNTL), in vcn_v2_0_start_dpg_mode()
1014 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); in vcn_v2_0_start()
1017 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp); in vcn_v2_0_start()
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| D | vcn_v2_5.c | 912 VCN, 0, mmUVD_MPC_CNTL), in vcn_v2_5_start_dpg_mode()
1064 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); in vcn_v2_5_start()
1067 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); in vcn_v2_5_start()
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| D | vcn_v3_0.c | 1032 VCN, inst_idx, mmUVD_MPC_CNTL), in vcn_v3_0_start_dpg_mode()
1194 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); in vcn_v3_0_start()
1197 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); in vcn_v3_0_start()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 344 #define mmUVD_MPC_CNTL … macro
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| D | vcn_2_5_offset.h | 757 #define mmUVD_MPC_CNTL … macro
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| D | vcn_2_0_0_offset.h | 592 #define mmUVD_MPC_CNTL … macro
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| D | vcn_3_0_0_offset.h | 1137 #define mmUVD_MPC_CNTL … macro
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