| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 43 #define mmUVD_GPCOM_VCPU_DATA0 0x3BC4 macro
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| D | uvd_4_2_d.h | 31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 macro
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| D | uvd_3_1_d.h | 31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 macro
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| D | uvd_5_0_d.h | 31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 macro
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| D | uvd_6_0_d.h | 31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 macro
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| D | uvd_7_0_offset.h | 56 #define mmUVD_GPCOM_VCPU_DATA0 … macro
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v6_0.c | 931 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_fence()
938 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_fence()
1068 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_wreg()
1081 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_vm_flush()
1096 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_pipeline_sync()
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| D | vcn_v1_0.c | 53 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
171 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); in vcn_v1_0_sw_init()
1474 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in vcn_v1_0_dec_ring_insert_start()
1518 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in vcn_v1_0_dec_ring_emit_fence()
1528 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in vcn_v1_0_dec_ring_emit_fence()
1578 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in vcn_v1_0_dec_ring_emit_reg_wait()
1612 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in vcn_v1_0_dec_ring_emit_wreg()
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| D | uvd_v3_1.c | 117 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v3_1_ring_emit_fence()
124 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v3_1_ring_emit_fence()
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| D | uvd_v4_2.c | 484 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v4_2_ring_emit_fence()
491 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v4_2_ring_emit_fence()
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| D | uvd_v5_0.c | 500 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v5_0_ring_emit_fence()
507 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v5_0_ring_emit_fence()
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| D | uvd_v7_0.c | 1191 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_fence()
1201 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_fence()
1373 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_wreg()
1389 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_reg_wait()
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| D | vcn_v2_0.c | 61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
188 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_0_sw_init()
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| D | vcn_v2_5.c | 64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
215 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_5_sw_init()
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| D | vcn_v3_0.c | 68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
208 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); in vcn_v3_0_sw_init()
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| D | amdgpu_uvd.c | 1008 case mmUVD_GPCOM_VCPU_DATA0: in amdgpu_uvd_cs_reg()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 140 #define mmUVD_GPCOM_VCPU_DATA0 … macro
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| D | vcn_2_5_offset.h | 513 #define mmUVD_GPCOM_VCPU_DATA0 … macro
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| D | vcn_2_0_0_offset.h | 812 #define mmUVD_GPCOM_VCPU_DATA0 … macro
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| D | vcn_3_0_0_offset.h | 829 #define mmUVD_GPCOM_VCPU_DATA0 … macro
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