Home
last modified time | relevance | path

Searched refs:mmUVD_DPG_LMA_CTL (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_vcn.h83 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
95 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
137 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
151 mmUVD_DPG_LMA_CTL, \
Damdgpu_jpeg.h42 mmUVD_DPG_LMA_CTL, \
56 WREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_CTL, \
Djpeg_v4_0_5.c37 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL macro
Dvcn_v4_0_5.c42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL macro
Dvcn_v4_0_3.c40 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL macro
Dvcn_v1_0.c78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),
Dvcn_v2_0.c86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),
Dvcn_v4_0.c42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL macro
Dvcn_v2_5.c89 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),
Dvcn_v3_0.c93 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h36 #define mmUVD_DPG_LMA_CTL macro
Dvcn_2_5_offset.h409 #define mmUVD_DPG_LMA_CTL macro
Dvcn_2_0_0_offset.h394 #define mmUVD_DPG_LMA_CTL macro
Dvcn_3_0_0_offset.h685 #define mmUVD_DPG_LMA_CTL macro