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Searched refs:mmUVD_CTX_INDEX (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h40 #define mmUVD_CTX_INDEX 0x3D28 macro
Duvd_4_2_d.h40 #define mmUVD_CTX_INDEX 0x3d28 macro
Duvd_3_1_d.h40 #define mmUVD_CTX_INDEX 0x3d28 macro
Duvd_5_0_d.h46 #define mmUVD_CTX_INDEX 0x3d28 macro
Duvd_6_0_d.h62 #define mmUVD_CTX_INDEX 0x3d28 macro
Duvd_7_0_offset.h140 #define mmUVD_CTX_INDEX macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h300 #define mmUVD_CTX_INDEX macro
Dvcn_2_5_offset.h603 #define mmUVD_CTX_INDEX macro
Dvcn_2_0_0_offset.h500 #define mmUVD_CTX_INDEX macro
Dvcn_3_0_0_offset.h939 #define mmUVD_CTX_INDEX macro
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dsoc15.c223 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); in soc15_uvd_ctx_rreg()
237 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); in soc15_uvd_ctx_wreg()
Dcik.c205 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_rreg()
216 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_wreg()
Dvi.c377 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in vi_uvd_ctx_rreg()
388 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in vi_uvd_ctx_wreg()
Dsi.c1096 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in si_uvd_ctx_rreg()
1107 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in si_uvd_ctx_wreg()