| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_4_0_d.h | 38 #define mmUVD_CONTEXT_ID 0x3DBD macro
|
| D | uvd_4_2_d.h | 81 #define mmUVD_CONTEXT_ID 0x3dbd macro
|
| D | uvd_3_1_d.h | 83 #define mmUVD_CONTEXT_ID 0x3dbd macro
|
| D | uvd_5_0_d.h | 87 #define mmUVD_CONTEXT_ID 0x3dbd macro
|
| D | uvd_6_0_d.h | 103 #define mmUVD_CONTEXT_ID 0x3dbd macro
|
| D | uvd_7_0_offset.h | 218 #define mmUVD_CONTEXT_ID … macro
|
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v3_1.c | 115 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_emit_fence()
146 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v3_1_ring_test_ring()
151 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_test_ring()
155 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v3_1_ring_test_ring()
|
| D | uvd_v4_2.c | 482 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v4_2_ring_emit_fence()
513 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v4_2_ring_test_ring()
518 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v4_2_ring_test_ring()
522 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v4_2_ring_test_ring()
|
| D | uvd_v5_0.c | 498 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v5_0_ring_emit_fence()
529 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v5_0_ring_test_ring()
533 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v5_0_ring_test_ring()
537 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v5_0_ring_test_ring()
|
| D | uvd_v6_0.c | 929 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v6_0_ring_emit_fence()
992 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v6_0_ring_test_ring()
997 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v6_0_ring_test_ring()
1001 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v6_0_ring_test_ring()
|
| D | uvd_v7_0.c | 1188 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); in uvd_v7_0_ring_emit_fence()
1258 WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v7_0_ring_test_ring()
1264 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); in uvd_v7_0_ring_test_ring()
1268 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID); in uvd_v7_0_ring_test_ring()
|
| D | vcn_v1_0.c | 51 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
1515 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); in vcn_v1_0_dec_ring_emit_fence()
|
| D | vcn_v2_0.c | 59 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
|
| D | vcn_v2_5.c | 62 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
|
| D | vcn_v3_0.c | 66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
|
| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 404 #define mmUVD_CONTEXT_ID … macro
|
| D | vcn_2_5_offset.h | 545 #define mmUVD_CONTEXT_ID … macro
|
| D | vcn_2_0_0_offset.h | 726 #define mmUVD_CONTEXT_ID … macro
|
| D | vcn_3_0_0_offset.h | 875 #define mmUVD_CONTEXT_ID … macro
|