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Searched refs:mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/sdma1/
Dsdma1_4_0_offset.h81 #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 macro
Dsdma1_4_2_offset.h81 #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX … macro
Dsdma1_4_2_2_offset.h81 #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX … macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h1063 #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX … macro
Dgc_10_3_0_offset.h1105 #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX … macro