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Searched refs:mmRLC_SPARE_INT_0_Sienna_Cichlid (Results 1 – 1 of 1) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 macro
4307 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); in gfx_v10_0_init_rlcg_reg_access_ctrl()