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Searched refs:mmRLC_PG_CNTL (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c3629 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pu()
3635 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_sclk_slowdown_on_pu()
3643 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pd()
3649 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_sclk_slowdown_on_pd()
3656 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_cp_pg()
3662 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_cp_pg()
3669 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gds_pg()
3675 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gds_pg()
3692 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_cgpg()
3695 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gfx_cgpg()
[all …]
Dgfx_v9_0.c2941 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_sck_slow_down_on_power_up()
2946 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_sck_slow_down_on_power_up()
2955 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_sck_slow_down_on_power_down()
2960 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_sck_slow_down_on_power_down()
2969 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_cp_power_gating()
2974 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_cp_power_gating()
2982 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_gfx_cg_power_gating()
2987 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_cg_power_gating()
2995 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_gfx_pipeline_powergating()
3000 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_pipeline_powergating()
[all …]
Dgfx_v6_0.c2649 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v6_0_enable_cp_pg()
2655 WREG32(mmRLC_PG_CNTL, data); in gfx_v6_0_enable_cp_pg()
2759 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v6_0_enable_gfx_static_mgpg()
2765 WREG32(mmRLC_PG_CNTL, data); in gfx_v6_0_enable_gfx_static_mgpg()
2773 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v6_0_enable_gfx_dynamic_mgpg()
2779 WREG32(mmRLC_PG_CNTL, data); in gfx_v6_0_enable_gfx_dynamic_mgpg()
Dgfx_v10_0.c5335 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); in gfx_v10_0_rlc_smu_handshake_cntl()
5349 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); in gfx_v10_0_rlc_smu_handshake_cntl()
5433 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); in gfx_v10_0_rlc_resume()
8250 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); in gfx_v10_cntl_power_gating()
8257 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); in gfx_v10_cntl_power_gating()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h1165 #define mmRLC_PG_CNTL 0x30D7 macro
Dgfx_7_2_d.h1288 #define mmRLC_PG_CNTL 0x3103 macro
Dgfx_7_0_d.h1275 #define mmRLC_PG_CNTL 0x3103 macro
Dgfx_8_0_d.h1386 #define mmRLC_PG_CNTL 0xec43 macro
Dgfx_8_1_d.h1388 #define mmRLC_PG_CNTL 0xec43 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6037 #define mmRLC_PG_CNTL … macro
Dgc_9_1_offset.h6259 #define mmRLC_PG_CNTL … macro
Dgc_9_2_1_offset.h6235 #define mmRLC_PG_CNTL … macro
Dgc_10_1_0_offset.h9385 #define mmRLC_PG_CNTL … macro
Dgc_10_3_0_offset.h9205 #define mmRLC_PG_CNTL … macro