Searched refs:mmRLC_MEM_SLP_CNTL (Results 1 – 14 of 14) sorted by relevance
| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_6_0_d.h | 1156 #define mmRLC_MEM_SLP_CNTL 0x30D8 macro
|
| D | gfx_7_2_d.h | 1260 #define mmRLC_MEM_SLP_CNTL 0x30c6 macro
|
| D | gfx_7_0_d.h | 1247 #define mmRLC_MEM_SLP_CNTL 0x30c6 macro
|
| D | gfx_8_0_d.h | 1349 #define mmRLC_MEM_SLP_CNTL 0xec06 macro
|
| D | gfx_8_1_d.h | 1351 #define mmRLC_MEM_SLP_CNTL 0xec06 macro
|
| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v9_0.c | 4942 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4945 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
4971 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4974 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
5288 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); in gfx_v9_0_get_clockgating_state()
|
| D | gfx_v8_0.c | 709 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
5465 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v8_0_get_clockgating_state()
5684 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v8_0_update_medium_grain_clock_gating()
5687 WREG32(mmRLC_MEM_SLP_CNTL, data); in gfx_v8_0_update_medium_grain_clock_gating()
|
| D | gfx_v7_0.c | 3578 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3581 WREG32(mmRLC_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
|
| D | gfx_v10_0.c | 7849 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
7852 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
7882 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
7885 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
8414 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); in gfx_v10_0_get_clockgating_state()
|
| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 5969 #define mmRLC_MEM_SLP_CNTL … macro
|
| D | gc_9_1_offset.h | 6191 #define mmRLC_MEM_SLP_CNTL … macro
|
| D | gc_9_2_1_offset.h | 6155 #define mmRLC_MEM_SLP_CNTL … macro
|
| D | gc_10_1_0_offset.h | 9301 #define mmRLC_MEM_SLP_CNTL … macro
|
| D | gc_10_3_0_offset.h | 9101 #define mmRLC_MEM_SLP_CNTL … macro
|