Home
last modified time | relevance | path

Searched refs:mmRLC_LB_CNTL (Results 1 – 14 of 14) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dsi.c111 mmRLC_LB_CNTL, 0xffffffff, 0x800000f4,
158 mmRLC_LB_CNTL, 0xffffffff, 0x800000a4,
295 mmRLC_LB_CNTL, 0xffffffff, 0x80010014,
380 mmRLC_LB_CNTL, 0xffffffff, 0x800000f4,
Dgfx_v7_0.c3248 tmp = RREG32(mmRLC_LB_CNTL); in gfx_v7_0_enable_lbpw()
3253 WREG32(mmRLC_LB_CNTL, tmp); in gfx_v7_0_enable_lbpw()
3440 WREG32(mmRLC_LB_CNTL, 0x80000004); in gfx_v7_0_rlc_resume()
Dgfx_v6_0.c2498 WREG32(mmRLC_LB_CNTL, 0); in gfx_v6_0_rlc_resume()
Dgfx_v9_0.c1741 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); in gfx_v9_0_init_lbpw()
1790 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); in gfx_v9_4_init_lbpw()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h1148 #define mmRLC_LB_CNTL 0x30C3 macro
Dgfx_7_2_d.h1269 #define mmRLC_LB_CNTL 0x30d9 macro
Dgfx_7_0_d.h1256 #define mmRLC_LB_CNTL 0x30d9 macro
Dgfx_8_0_d.h1363 #define mmRLC_LB_CNTL 0xec19 macro
Dgfx_8_1_d.h1366 #define mmRLC_LB_CNTL 0xec19 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6003 #define mmRLC_LB_CNTL macro
Dgc_9_1_offset.h6225 #define mmRLC_LB_CNTL macro
Dgc_9_2_1_offset.h6189 #define mmRLC_LB_CNTL macro
Dgc_10_1_0_offset.h9331 #define mmRLC_LB_CNTL macro
Dgc_10_3_0_offset.h9135 #define mmRLC_LB_CNTL macro