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Searched refs:mmOTG3_OTG_COUNT_CONTROL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_1_offset.h7207 #define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX … macro
Ddcn_1_0_offset.h7002 #define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX … macro
Ddcn_2_1_0_offset.h8648 #define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX … macro
Ddcn_3_0_2_offset.h8556 #define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX … macro
Ddcn_2_0_0_offset.h9679 #define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX … macro
Ddcn_3_0_0_offset.h9416 #define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX … macro