Searched refs:mmNIC0_QM0_GLBL_CFG0 (Results 1 – 4 of 4) sorted by relevance
22 #define mmNIC0_QM0_GLBL_CFG0 0xCE0000 macro
23 #define mmNIC0_QM0_GLBL_CFG0 0x541A000 macro
1635 WREG32(mmNIC0_QM0_GLBL_CFG0, 0); in gaudi_late_init()3239 mmNIC0_QM1_GLBL_CFG0 - mmNIC0_QM0_GLBL_CFG0; in gaudi_init_nic_qmans()3241 mmNIC1_QM0_GLBL_CFG0 - mmNIC0_QM0_GLBL_CFG0; in gaudi_init_nic_qmans()3272 WREG32(mmNIC0_QM0_GLBL_CFG0 + nic_offset, NIC_QMAN_ENABLE); in gaudi_init_nic_qmans()3341 mmNIC0_QM1_GLBL_CFG0 - mmNIC0_QM0_GLBL_CFG0; in gaudi_disable_nic_qmans()3343 mmNIC1_QM0_GLBL_CFG0 - mmNIC0_QM0_GLBL_CFG0; in gaudi_disable_nic_qmans()3350 WREG32(mmNIC0_QM0_GLBL_CFG0 + nic_offset, 0); in gaudi_disable_nic_qmans()
5195 pb_addr = (mmNIC0_QM0_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS; in gaudi_init_nic_protection_bits()5196 word_offset = ((mmNIC0_QM0_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2; in gaudi_init_nic_protection_bits()5197 mask = 1U << ((mmNIC0_QM0_GLBL_CFG0 & 0x7F) >> 2); in gaudi_init_nic_protection_bits()