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Searched refs:mmMC_SEQ_WR_CTL_2_LP (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_6_0_d.h1002 #define mmMC_SEQ_WR_CTL_2_LP 0x0AD6 macro
Dgmc_7_1_d.h820 #define mmMC_SEQ_WR_CTL_2_LP 0xad6 macro
Dgmc_8_1_d.h924 #define mmMC_SEQ_WR_CTL_2_LP 0xad6 macro
/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Diceland_smumgr.c2457 *out_reg = mmMC_SEQ_WR_CTL_2_LP; in iceland_check_s0_mc_reg_index()
2636 …cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_… in iceland_initialize_mc_reg_table()
Dci_smumgr.c2530 *out_reg = mmMC_SEQ_WR_CTL_2_LP; in ci_check_s0_mc_reg_index()
2709 …cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_… in ci_initialize_mc_reg_table()
Dtonga_smumgr.c2919 *out_reg = mmMC_SEQ_WR_CTL_2_LP; in tonga_check_s0_mc_reg_index()
3119 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, in tonga_initialize_mc_reg_table()