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Searched refs:mmMC_SEQ_SUP_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgmc_v8_0.c303 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_tonga_mc_load_microcode()
307 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
308 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_tonga_mc_load_microcode()
320 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_tonga_mc_load_microcode()
321 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v8_0_tonga_mc_load_microcode()
322 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v8_0_tonga_mc_load_microcode()
382 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_polaris_mc_load_microcode()
383 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v8_0_polaris_mc_load_microcode()
390 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v8_0_polaris_mc_load_microcode()
391 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v8_0_polaris_mc_load_microcode()
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Dgmc_v6_0.c162 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; in gmc_v6_0_mc_load_microcode()
167 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
168 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v6_0_mc_load_microcode()
180 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v6_0_mc_load_microcode()
181 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v6_0_mc_load_microcode()
182 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v6_0_mc_load_microcode()
Dgmc_v7_0.c193 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
197 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
198 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); in gmc_v7_0_mc_load_microcode()
210 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); in gmc_v7_0_mc_load_microcode()
211 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); in gmc_v7_0_mc_load_microcode()
212 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); in gmc_v7_0_mc_load_microcode()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_6_0_d.h949 #define mmMC_SEQ_SUP_CNTL 0x0A32 macro
Dgmc_7_1_d.h784 #define mmMC_SEQ_SUP_CNTL 0xa32 macro
Dgmc_8_1_d.h888 #define mmMC_SEQ_SUP_CNTL 0xa32 macro