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Searched refs:mmINPUT_CSC_CONTROL (Results 1 – 9 of 9) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Ddce_v10_0.c2119 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2122 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
Ddce_v11_0.c2169 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2171 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
Ddce_v6_0.c2076 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
Ddce_v8_0.c2043 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_load_lut()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h3874 #define mmINPUT_CSC_CONTROL 0x1A35 macro
Ddce_8_0_d.h1899 #define mmINPUT_CSC_CONTROL 0x1a35 macro
Ddce_10_0_d.h2748 #define mmINPUT_CSC_CONTROL 0x1a35 macro
Ddce_11_0_d.h2502 #define mmINPUT_CSC_CONTROL 0x1a35 macro
Ddce_11_2_d.h3733 #define mmINPUT_CSC_CONTROL 0x1a35 macro