Searched refs:mmHDMI_ACR_48_0 (Results 1 – 9 of 9) sorted by relevance
1456 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v6_0_audio_set_acr()1458 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1505 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()1507 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1554 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()1556 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1478 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT)); in dce_v8_0_afmt_update_ACR()
3854 #define mmHDMI_ACR_48_0 0x1C3B macro
3215 #define mmHDMI_ACR_48_0 0x1c3b macro
3994 #define mmHDMI_ACR_48_0 0x4a32 macro
3867 #define mmHDMI_ACR_48_0 0x4a32 macro
5098 #define mmHDMI_ACR_48_0 0x4a32 macro