Searched refs:mmGRPH_PRIMARY_SURFACE_ADDRESS (Results 1 – 9 of 9) sorted by relevance
209 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()213 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v6_0_page_flip()1989 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
201 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v8_0_page_flip()204 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v8_0_page_flip()1958 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_do_set_base()
253 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_page_flip()256 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()2028 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
277 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()280 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()2078 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
3835 #define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1A04 macro
1563 #define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 macro
2412 #define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 macro
2306 #define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 macro
3537 #define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 macro