Searched refs:mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR (Results 1 – 5 of 5) sorted by relevance
120 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040 macro
294 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040 macro
1097 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_qman()1099 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_qman()1140 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_ch()1142 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_ch()1366 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, in goya_init_cpu_queues()1838 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_qman()1840 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_qman()1887 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_cmdq()1889 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_cmdq()1945 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_tpc_qman()[all …]
165 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x4800040 macro
2603 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_pci_dma_qman()2658 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_dma_core()2774 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_hbm_dma_qman()2907 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_mme_qman()3043 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_tpc_qman()3200 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_nic_qman()3857 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_cpu_queues()4048 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_hw_fini()4513 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_ring_doorbell()8783 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_enable_events_from_fw()