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Searched refs:mmDSCL1_SCL_TAP_CONTROL_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_offset.h1988 #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX … macro
Ddcn_3_0_3_offset.h3244 #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX … macro
Ddcn_3_0_1_offset.h4055 #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX … macro
Ddcn_1_0_offset.h3993 #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX … macro
Ddcn_2_1_0_offset.h3943 #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX … macro
Ddcn_3_0_2_offset.h4600 #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX … macro
Ddcn_2_0_0_offset.h4881 #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX … macro
Ddcn_3_0_0_offset.h4651 #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX … macro